高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

Mobility enhancement of strained GaSb p-channel metal oxide semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal–oxide–semiconductor field-effect transistors(MOSFETs)are experimentally and theoretically investigated. The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm~2/V·s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain.Meanwhile, first principles calculations show that the hole effective mass of Ga Sb depends on the biaxial compressive strain.The biaxial compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

电离辐射环境下的部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管可靠性研究

随着半导体技术的进步, 集成小尺寸绝缘体上硅器件的芯片开始应用到航空航天领域, 使得器件在使用中面临了深空辐射环境与自身常规可靠性的双重挑战. 进行小尺寸器件电离辐射环境下的可靠性试验有助于对器件综合可靠性进行评估. 参照国标GB2689.1-81恒定应力寿命试验与加速寿命试验方法总则进行电应力选取, 对部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管进行了电离辐射环境下的常规可靠性研究. 通过试验对比, 定性地分析了氧化物陷阱电荷和界面态对器件敏感参数的影响, 得出了氧化物陷阱电荷和界面态随着时间参数的变化, 在不同阶段对器件参数的影响. 结果表明, 总剂量效应与电应力的共同作用将加剧器件敏感参数的退化, 二者的共同作用远大于单一影响因子.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

A model for the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor

An improved theoretical model on the electrical characteristics of metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) has been proposed by considering the history-dependent electric field effect and the mobility model. The capacitance-voltage (C-V) characteristics of MFIS structure is evaluated by combining the switching physics of ferroelectric with the silicon physics, and the drain current-gate voltage (I_D-V_GS) and drain current-drain voltage (I_D-V_DS) characteristics of MFIS-FET are modeled by combining the switching physics of ferroelectric with Pao and Sah’s double integral. For two MFIS-FETs with SrBi₂Ta₂O₉ and (Bi,La)₄Ti₃O₁₂ ferroelectric layers, the C-V, I_D-V_GS and I_D-V_DS characteristics are simulated by using the improved model, and the results are more consistent with the previous experiment than those based on Lue model, indicating that the improved model is suitable for simulating the electrical characteristics of MFIS-FET. This work is expected to provide some guidance to the design and performance improvement of MFIS structure devices.     

High temperature characteristics of bilayer epitaxial graphene field-effect transistors on SiC Substrate

In this paper,high temperature direct current(DC) performance of bilayer epitaxial graphene device on SiC substrate is studied in a temperature range from 25℃ to 200℃.At a gate voltage of-8 V(far from Dirac point),the drainsource current decreases obviously with increasing temperature,but it has little change at a gate bias of +8 V(near Dirac point).The competing interactions between scattering and thermal activation are responsible for the different reduction tendencies.Four different kinds of scatterings are taken into account to qualitatively analyze the carrier mobility under different temperatures.The devices exhibit almost unchanged DC performances after high temperature measurements at 200℃ for 5 hours in air ambience,demonstrating the high thermal stabilities of the bilayer epitaxial graphene devices.     

Temperature dependent conductive behavior of pentacene in organic field-effect transistor

Impedance characterization at different temperature has been used to investigate the conductive behavior of pentacene as the semiconductor layer in organic field-effect transistor. It has been found that the pentacene exhibits an enhancement in conductivity by heating following an Arrhenius law with an activation energy transition from 0.004 to 0.018 eV at 323 K, which originates from band tail hopping that occurs around the Fermi edge.     

p型金属氧化物半导体场效应晶体管低剂量率辐射损伤增强效应模型研究

对一种非加固4007电路中p型金属氧化物半导体场效应晶体管(PMOSFET)在不同剂量率条件下的电离辐射损伤效应及高剂量率辐照后的退火效应进行了研究. 通过测量不同剂量率条件下PMOSFET的亚阈I-V特性曲线,得到阈值电压漂移量随累积剂量、退火时间的变化关系. 实验发现,此种型号的PMOSFET具有低剂量率辐射损伤增强效应. 通过描述H⁺在氧化层中的输运过程,解释了界面态的形成原因,初步探讨了非加固4007电路中PMOSFET低剂量率辐射损伤增强效应模型. 关键词： p型金属氧化物半导体场效应晶体管 60Co γ射线')" href="#">⁶⁰Co γ射线 电离辐射损伤 低剂量率辐射损伤增强效应     

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/AlO_x gated Al Ga N/Ga N metal–oxide–semiconductor heterostructure field-effect transistors(MOSHFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600℃ with the contact resistance approximately 1.6 ?·mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/AlO_x gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate Al Ga N/Ga N MOS-HFETs.     

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors(MOSCAPs) with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density Ditof the HfAlO/GaSb interface by 35% and reduce the equivalent oxide thickness(EOT) from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy(HRXTEM) results. It was also found that GaSb-based MOSCAPs with HfAlO gate dielectrics have interfacial properties superior to those using HfO2 or Al2O3 dielectric layers.     

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H–Si C metal–oxide–semiconductor field-effect transistors(MOSFFETs) have been fabricated and characterized. A sandwich-(nitridation–oxidation–nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H–Si C/SiO_2 were examined by the measurement of HF I–V, G–V, and C–V over a range of frequencies. The ideal C–V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H–Si C was reduced to 2 × 10~(11) e V~(-1)·cm~(-2), the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak fieldeffect mobility is about 32.5 cm~2·V~(-1)·s~(-1), and the maximum peak field-effect mobility of 38 cm~2·V~(-1)·s~(-1) was achieved in fabricated lateral 4H–Si C MOSFFETs.     

深亚微米金属氧化物场效应晶体管及寄生双极晶体管的总剂量效应研究

为从工艺角度深入研究航空航天用互补金属氧化物半导体(CMOS)工艺混合信号集成电路总剂量辐射损伤机理, 选取国产CMOS 工艺制作的NMOS晶体管及寄生双极晶体管进行了⁶⁰Coγ射线源下的总剂量试验研究. 发现: 1) CMOS工艺中固有的寄生效应导致NMOS晶体管截止区漏电流对总剂量敏感, 随总剂量累积而增 大; 2) 寄生双极晶体管总剂量损伤与常规双极晶体管不同, 表现为对总剂量不敏感, 分析认为两者辐射损伤的差异来源于制作工艺的不同; 3)寄生双极晶体管与NMOS晶体 管的总剂量损伤没有耦合效应; 4)基于上述研究成果, 初步分析CMOS工艺混合信号集成电路中数字模块及模拟模块辐射损伤机制, 认为MOS晶体管截止漏电流增大是导致数字模块功耗增大的主因, 而Bandgap电压基准源模块对总剂量不敏感源于寄生双极晶体管抗总剂量辐射的能力. 关键词： 总剂量效应 N沟道金属氧化物场效应晶体管 寄生双极晶体管 Bandgap基准电压源     

U型槽刻蚀工艺对GaN垂直沟槽型金属-氧化物-半导体场效应晶体管电学特性的影响

U型槽的干法刻蚀工艺是GaN垂直沟槽型金属-氧化物-半导体场效应晶体管(MOSFET)器件关键的工艺步骤,干法刻蚀后GaN的侧壁状况直接影响GaN MOS结构中的界面态特性和器件的沟道电子输运.本文通过改变感应耦合等离子体干法刻蚀工艺中的射频功率和刻蚀掩模,研究了GaN垂直沟槽型MOSFET电学特性的工艺依赖性.研究结果表明,适当降低射频功率,在保证侧壁陡直的前提下可以改善沟道电子迁移率,从35.7 cm^2/(V·s)提高到48.1 cm^2/(V·s),并提高器件的工作电流.沟道处的界面态密度可以通过亚阈值摆幅提取,射频功率在50 W时界面态密度降低到1.90×10^12 cm^-2·eV^-1,比135 W条件下降低了一半.采用SiO2硬刻蚀掩模代替光刻胶掩模可以提高沟槽底部的刻蚀均匀性.较薄的SiO2掩模具有更小的侧壁面积,高能离子的反射作用更弱,过刻蚀现象明显改善,制备出的GaN垂直沟槽型MOSFET沟道场效应迁移率更高,界面态密度更低.     

高功率微波作用下热载流子引起n型金属-氧化物-半导体场效应晶体管特性退化研究

高功率微波(HPM)通过使半导体器件特性退化和功能失效,从而干扰电子系统无法正常工作. 针对金属氧化物半导体(MOS)器件的HPM效应, 建立了高功率微波引起n型金属氧化物半导体场效应晶体管(nMOSFET)特性退化的物理过程与模型. 器件仿真结果中nMOSFET的输出特性曲线显示栅极注入HPM引起器件特性退化,包括阈值电压正向漂移、 饱和电流减小、跨导减小等;结合物理模型分析可知, HPM引起的高频脉冲电压使器件进入深耗尽状态, 热载流子数目增多,热载流子效应导致器件特性退化. MOS器件的HPM注入实验结果显示,器件特性曲线、器件模型参数变化趋势与仿真结果一致, 验证了HPM引起nMOSFET特性退化的物理过程与模型.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Dual-gated BN-sandwiched multilayer graphene field-effect transistor fabricated by stamping transfer method and self-aligned contact

To fabricate a BN-sandwiched multilayer graphene field-effect transistor, we developed a self-aligned contact scheme in combination with optimized stamping processes for the stacking of two-dimensional (2D) materials. By using a self-aligned contact method during device fabrication, we can skip the dry-etch process which requires an exact etch-stop at the surface of the graphene layer and is not easy to control. In the structure of a dual-gate transistor, successful device operation at low temperature with and without magnetic fields proves that the self-alignment contact can be an effective tool for reliable device fabrication using 2D materials.     

Study of top and bottom contact resistance in one organic field-effect transistor

This paper reports that the organic field-effect transistors with hybrid contact geometry were fabricated, in which the top electrodes and the bottom electrodes were combined in parallel resistances within one transistor. With the facility of the novel structure, the difference of contact resistance between the top contact geometry and the bottom contact geometry was studied. The hybrid contact devices showed similar characteristics with the top contact configuration devices, which provide helpful evidence on the lower contact resistance of the top contact configuration device. The origin of the different contact resistance between the top contact device and the bottom contact device was discussed.     

Electrical characteristics of MOS capacitor with HfTiON gate dielectric and HfTiSiON interlayer

The paper reports that HfTiO dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O₂ ambience, followed by an annealing in different gas ambiences of N₂, NO and NH₃ at 600℃ for 2 min. Capacitance--voltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si \equiv N bonds to passivate dangling Si bonds and replace strained Si--O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.