共查询到19条相似文献,搜索用时 140 毫秒
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分析了混合信号边界扫描测试的工作机制对测试系统的功能需求,实现了符合IEEE1149.4标准的混合信号边界扫描测试系统。仿真和测试实践表明,该测试系统具有对系统级、PCB级和芯片级电路进行简单互连测试、差分测试和参数测试等功能,结构简单、携带方便、工作可靠。 相似文献
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缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法. 相似文献
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本文针对固定管脚芯片可测性设计中测试向量庞大和测试时间过长问题,提出了一种有效的压缩可测性设计,改进了传统并行扫描测试设计。该设计方法在SMIC 0.18μm工艺下一款电力载波通信芯片设计中验证,仿真结果表明压缩扫描可测性设计能有效减少测试向量数目,从而减小芯片测试时间。 相似文献
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使用本院CAT研究室开发的混合信号边界扫描测试系统对KLIC实验芯片进行简单互连、扩展互连测试和CLUSTER测试。通过对测试结果的分析表明,IEEE1149.4测试总线在这些测试中是非常成功的,同时指出其局限性。 相似文献
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PXI Express为PXI仪器平台增添了众多的技术优势,开辟了许多新兴测量领域.PXI Express仪器系统提供的高达2GB/s的数据吞吐量使得以前只能通过定制硬件或是昂贵的专用仪器才能实现的高速测量应用变为可能. 相似文献
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Nur Engin Hans G. Kerkhoff Ronald J.W.T. Tangelder Han Speek 《Journal of Electronic Testing》1999,14(1-2):75-83
In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed. 相似文献
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介绍了一种基于二分算法的混合信号接口板.该接口板可通过编程任意配置测试芯片管脚实现模拟或数字信号输入端口与输出端口的无损连接,可广泛应用于芯片自动化测试领域.本设计采用二分法来实现管脚的分级,采用遍历引脚逐一比较的方式来配置引脚连接,通过控制模拟开关阵列来实现模拟信号的输入与输出端口连接,通过FPGA实现数字信号的输入与输出端口连接.该设计方案利用极少的开关实现了复杂线路的配置,具有较高的资源利用率,极大降低了芯片测试的难度和成本. 相似文献
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正电子发射断层成像系统(PET)前端读出电路是数模混合信号超大规模集成电路芯片.针对多通道高性能PET专用集成电路芯片的特点,采用JTAG控制器对该芯片进行初始控制和辅助测试.采用TSMC 0.18μmCMOS工艺设计实现了一个可扩展的JTAG控制器IP核,支持14组可扩展控制信号和16个多位寄存器扫描链的读/写操作,并配备定制的底层驱动软件.该JTAG控制器IP核还可用于其它混合信号VLSI的控制与测试,具有较强的通用性和工程实用价值. 相似文献
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利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。 相似文献
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A new Built-In Self-Test structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A Digital Signature is obtained which is used to discriminate catastrophic as well as parametric defects. High Fault Coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature. 相似文献
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This paper presents the design and analysis of a built-in tester circuit for MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length significantly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comparator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 W, and a layout area of 0.01 mm2, where the circuit is simulated with the MOSIS SCN 2 m CMOS process parameters and 2 V supply voltage. 相似文献