Selectively silicided vertical power DMOSFETs for high-frequency power conversion

A 50 V, 0.56 m Omega cm/sup 2/ vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering the gate sheet resistance compared with the conventional heavily doped n/sup +/-polysilicon gates. Devices with cell density as high as 8 million cells/inch/sup 2/ and die size as large as 200 mil*220 mil and capable of conducting more than 160 A of current have been successfully fabricated with excellent gate yield. These results represent the highest reported forward conductivities for any type of power FET in the 50 V reverse blocking range.<>     

An accurate photonic capacitance model for GaAs MESFETs

A new set of pseudoempirical equations is presented in order to simulate the optical and bias dependencies of GaAs MESFET junction capacitances, which is valid for the whole I-V plane. The variations induced in the small-signal equivalent circuit by the optical illumination are extracted from on-wafer scattering parameter measurements. New linear and quasi-logarithmic variations versus the incident optical power are shown for gate-drain and gate-source (Cgd and Cgs) capacitances. Furthermore, experimental results are in very good agreement with the simulated values for a wide range of optical power and bias conditions. Large signal MESFET models show a better fit with measured S-parameters than those previously published, leading to a greater degree of confidence in the design of photonic monolithic microwave integrated circuits     

An accurate 2-D hard-source model for FDTD

This letter describes an accurate two-dimensional (2-D) hard-source model for finite-difference time-domain (FDTD). The proposed model allows accurate control over the effective radius of a 2-D hard source. In addition, the TM version of the source model is directly applicable as a very accurate 2-D thin-wire model. The proposed model is verified in 2-D for both TM and TE case using a recently introduced method for finding the effective radius of a filamentary 2-D hard source     

An accurate small-signal model for AlGaN-GaNHEMT suitable for scalable large-signal model construction

The validity of the proposed small-signal model (SSM) and the developed extraction method in for large GaN devices is investigated. Extraction of parasitic elements is performed for different size devices to show the scaling of these elements with the gate width. The model shows a very good result for describing the parasitic distributed effect, which is considerable for large devices.     

An accurate JFET/MESFET model for circuit analysis

An accurate model for junction field-effect transistors (JFETs) and for Schottky barrier field-effect transistors (MESFETs) with micron and submicron dimensions is presented. The following effects are modeled: distributed channel charge, electrostatic drain feedback, drift velocity saturation, channel length modulation, substrate bias effect, subthreshold region effect, short-length and narrow-width effects, drain-source punch-through, variable capacitance effects, and temperature effects. It is primarily physical rather than empirical and only one set of parameters is needed to simulate devices of a particular technology. The model is intended for silicon devices, but the extension to devices in semiconducting III–V compounds and with insulating substrates is straightforward. The model is compared to experimental data.     

An accurate semi-empirical saturation drain current model for LDDn-MOSFET

Based on a new empirical mobility model which is solely dependent on V_gs, V_t and T_ox, a corresponding semiempirical I_dsat model for n-MOSFET including velocity saturation, mobility degradation due to increased vertical effective field, and source/drain series resistance of LDD structures is reported in this paper. A good agreement among the model and the measurement data from several different technologies is shown. Prediction of I_dsat for the future generations of device scaling and low-power applications by using this new model is presented     

An accurate theoretical model for the thin-wire circular half-loopantenna

The conventional Fourier series analysis for the thin-wire circular transmitting loop, or its image equivalent to the half-loop, uses a delta-function generator for excitation. This method of excitation introduces two problems: it does not correspond to any realizable method of feeding the antenna, so an accurate comparison with measurement is not possible, and it produces a divergent series for the input susceptance. To overcome these problems, a new theoretical model is used for the antenna: a half-loop driven through an image plane by a coaxial transmission line, with a transverse electromagnetic mode assumed in the aperture of the coaxial line. This model is solved in a manner that preserves the simplicity of the original Fourier series analysis. All coefficients are obtained as closed-form expressions. Input admittances calculated from this new theoretical model are in excellent agreement with accurate measurements     

An accurate nonlinear MOSFET model for intermodulation distortion analysis

A compact charge-conservative nonlinear equivalent circuit model for metal-oxide-semiconductor field-effect transistors is comprehensively verified in terms of its ability to predict intermodulation distortion. The model is valid for the dc, small-signal, and large-signal simulation of high frequency circuits over a wide range of bias conditions and is globally fully continuous. Simulations made using the model, following parameter extraction, are validated by comparisons with experimental data. Using harmonic balance methods, intermodulation distortion for weak and large-signal two-tone tests and more realistic wide-band code-division-multiple-access signals is successfully predicted for a range of bias points.     

An accurate error analysis model for fast Fourier transform

An error propagation model is proposed for the in-place decimation-in-time version of the radix-2 FFT algorithm. With the model, an accurate error expression and error variance for the computation of FFT are derived. This correspondence deals with fixed-point and block floating-point arithmetic. Simulation results agree closely with the theoretical predicted ones. We find that some roundoff errors at different stages correlate with each other. The density of correlations is closely associated with the round-off approach used in butterfly calculations     

An accurate thin-wire model for 3-D TLM simulations

Accurate modeling of thin wires in large-scale numerical electromagnetic simulations is very time consuming if fine meshing is adopted. Special treatments of such wires to allow their incorporation into relatively coarse meshes have lead to the development of thin-wire nodes for the transmission-line matrix (TLM) method. Previous models require the use of empirical factors. A novel thin-wire node is presented that is derived from rigorous field theory, requires no empirical factors and is shown to be highly effective. Moreover, virtually no computational overhead is incurred in the use of the new wire node.     

The lumped-charge power MOSFET model, including parameterextraction

A fundamentally new, physically-based power MOSFET model features continuous and accurate curves for all three interelectrode capacitances. The model equations are derived from the charge stored on two internal nodes and the three external terminals. A straightforward parameter extraction technique uses the standard gate-charge plot or process data and is matched with interelectrode capacitance measurements. Simulations are in excellent agreement with measurements. The model is used to design a snubber for a flyback converter     

An accurate moment method model for the tapered slot antenna

A moment-method model is presented for the radiation characteristics of the tapered slot antenna. It overcomes the shortcoming of an earlier theory. The method is rigorous for the air dielectric antennas. For dielectric-supported antennas, the method is approximate but accurate. The method is particularly accurate for antennas etched on substrates that are electrically thin or have a low dielectric constant, within the limits of (ε_r-1)d /λ₀⩽0.1. Numerical results are presented for the radiation pattern and compared with experimental results to validate the model     

An accurate electro-thermal model for merged SiC PiN Schottky diodes

The paper presents a SiC merged PiN Schottky diode model dedicated to the dynamic as-well-as very accurate static simulation. The model takes into account the temperature dependence of device characteristics and combines in a single model the behaviour typical for bipolar and unipolar devices. The presented electro-thermal simulations of the diode produce accurate results, consistent with the measurements. The dynamic model verification has been also presented on the example of a boost power converter.     

An accurate analytical propagation delay model for high-speed CMLbipolar circuits

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i₀ (or load resistor R_L) for a transistor of a certain emitter area when driven by a source of a voltage swing (ΔV) and slew time (t_r ). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits     

An accurate HJFET capacitance-voltage model for implementation witha circuit simulator

We present a new accurate HJFET capacitance model to implement with a circuit simulator. This is an analytical model that describes capacitance-voltage (C-V) characteristics over a wide supply voltage range. The model for a capacitance component due to two-dimensional electron gas (2-DEG) conduction is based on gradual channel approximation, and takes into account the gradual capacitance transition near the threshold voltage. It also takes into account the field dependence of the 2-DEG mobility, which is very strong for deep sub-micron devices. The model for parasitic MESFET capacitance is based on the formula for a Schottky diode. Since the model consists of physical parameters, it provides feedback between the fabrication process and circuit design. The simulated results agree well with the measurements     

双根锥形硅通孔结构的精确RLGC电路模型

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.     

An accurate model of domain-wall-based spintronic memristor

Spintronic memristors are promising devices that can be used in various applications such as memory chips and neuromorphic systems. The spintronic memristor combines the non-volatility advantage of resistive memristors, and the good scalability, and radiation hardness of spin-transfer torque magnetic devices. In addition, spintronic memristors can benefit from the maturity of integrating magnetic devices on top of CMOS devices. Current models of spintronic memristor only provide a similar version of the linear ion drift model of resistive memristors, which offers a simplified model, but with low accuracy and without enough linking to the device's physical parameters. In this paper, an accurate model of domain-wall- based spintronic memristor based on Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation is proposed. The proposed model provides a more accurate dynamical behavior by using the LLGS equation, and better relation to the device's physical parameters. It also uses the required equations that cover different types and geometries of spintronic memristors. The effect of the thermal fluctuations on device's parameters is also included into the model. The model uses the theory of domain-wall motion to explain the behavior of the device. Furthermore, a Verilog-A model is developed in order be compatible with IC CAD tools.     

An accurate analysis of noise in rectangular bipolar transistors including current crowding

An accurate analysis of noise in rectangular bipolar transistors is developed from a distributed model using a collective approach and the transport noise theory. In this model, emitter current crowding effect are taken into account and noise behaviour at intermediate and low values of source impedance is precisely described. The structure of teh equivalent lumped circuit is established, and the analytical relationships characterizing its elements in an extended range of current and frequency are given. It is shown that; (a) the active base region must be represented by a nonlinear impedance with a generalized thermal noise source; (b) for low source impedances the equivalent input voltage shot noise generator is higher than predicted by low injection theories. Furthermore it is found that emitter crowding induces a uniform and important decrease in (a) base impedance (b) thermal noise and (c) the correlation between shot noise generators of the equivalent lumped circuit. Finally it appears that classical low injection theories are valid when crowding occurs in transistors biased with high source impedances.