Metal-oxide-semiconductor field effect transistor using ‘oxidizedμc-Si/ultrathin oxide’ gate structure

The metal-oxide-semiconductor (MOS) field effect transistor (FET) using ‘oxidized μ c-Si/ultrathin oxide’ gate structure was studied. It was found that this structure shows negative differential resistance behavior, which can be explained by the Coulomb blockade effect of trapped carriers and immediate tunneling into and tunneling out with gate bias variation. The requirements for the device with this structure showing negative differential resistance behavior are based on very weak resistive coupling between floating gate and channel. They are the thinness of the tunnel oxide film, the thickness ratio of the upper oxidized film and the tunnel oxide, and the channel threshold voltage. MOSFET with this gate structure is proposed as a new negative differential resistance device.     

Study of density of interface states in MOS structure with ultrathin NAOS oxide

The quality of the interface region in a semiconductor device and the density of interface states (DOS) play important roles and become critical for the quality of the whole device containing ultrathin oxide films. In the present study the metal-oxide-semiconductor (MOS) structures with ultrathin SiO₂ layer were prepared on Si(100) substrates by using a low temperature nitric acid oxidation of silicon (NAOS) method. Carrier confinement in the structure produces the space quantization effect important for localization of carriers in the structure and determination of the capacitance. We determined the DOS by using the theoretical capacitance of the MOS structure computed by the quantum mechanical approach. The development of the density of SiO₂/Si interface states was analyzed by theoretical modeling of the C-V curves, based on the superposition of theoretical capacitance without interface states and additional capacitance corresponding to the charges trapped by the interface states. The development of the DOS distribution with the passivation procedures can be determined by this method.     

Hot carrier degradation mechanism interpretation by lateral distribution of interface and bulk trap density

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density (N_it) and bulk trapped charge density (N_ot) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with N_it and N_ot profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters N_it and N_ot. We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and N_it and N_ot profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.     

基于辐照前1/f噪声的金属-氧化物-半导体场效应晶体管辐照退化模型

基于金属-氧化物-半导体场效应晶体管(MOSFET)噪声的载流子数涨落和迁移率涨落理论,建立了MOSFET辐照前1/f噪声参量与辐照后分别由氧化层陷阱和界面陷阱诱使阈值电压漂移之间的定量数学模型,并通过实验予以验证.研究结果表明,辐照诱生的氧化层陷阱通过俘获和发射过程与沟道交换载流子,在引起载流子数涨落的同时也通过库仑散射导致沟道迁移率的涨落,因此辐照前的1/f噪声幅值正比于辐照诱生的氧化层陷阱数.利用该模型对MOSFET辐照前1/f噪声与辐照退化的相关性从理论上 关键词： f噪声')" href="#">1/f噪声 辐照 金属-氧化物-半导体场效应晶体管 陷阱     

Dual-Material Surrounding-Gate Metal-Oxide-Semiconductor Field Effect Transistors with Asymmetric Halo

Asymmetrical halo and dual-material gate structure are used in the sub-100 nm surrounding-gate metal oxidesemiconductor field effect transistor （MOSFET） to improve the performance. Using three-region parabolic potential distribution and universal boundary condition, analytical surface potential and threshold voltage models of the novel MOSFET are developed based on the solution of Poisson＇s equation. The performance of the MOS- FET is examined by the analytical models and the 3D numerical device simulator Davinci. It is shown that the novel MOSFET can suppress short channel effect and improve carrier transport efficiency. The derived analytical models agree well with Davinci.     

C-V法提取SiC隐埋沟道MOSFET沟道载流子浓度

本文对用C-V法提取SiC隐埋沟道MOSFET沟道载流子浓度的方法进行了理论和实验分析. pn结的存在所造成的埋沟MOS结构C-V曲线的畸变为沟道载流子浓度的提取带来一些问题. SiC/SiO₂界面上界面态的存在也会使提取出的数值与实际数值产生偏差. 本文首先从理论上分别分析了沟道深度和界面态对沟道载流子浓度提取结果的影响，然后对两种沟道深度的埋沟MOS结构C-V曲线进行了测试，提取出了沟道掺杂浓度. 在测试中，采用不同的扫描速率，分析了界面态对提取结果的影响. 理论分析结果和实验测 关键词： C-V法 SiC 隐埋沟道MOSFET 沟道载流子浓度     

Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high-<Emphasis Type="Italic">K</Emphasis> gate dielectric impacts on the inversion charge density

The comparison of the inversion electron density between a nanometer metal-oxide-semiconductor (MOS) device with high-K gate dielectric and a SiO₂ MOS device with the same equivalent oxide thickness has been discussed. A fully self-consistent solution of the coupled Schr?dinger–Poisson equations demonstrates that a larger dielectric-constant mismatch between the gate dielectric and silicon substrate can reduce electron density in the channel of a MOS device under inversion bias. Such a reduction in inversion electron density of the channel will increase with increase in gate voltage. A reduction in the charge density implies a reduction in the inversion electron density in the channel of a MOS device. It also implies that a larger dielectric constant of the gate dielectric might result in a reduction in the source–drain current and the gate leakage current.     

单轴应变Si NMOSFET热载流子栅电流模型

热载流子效应产生的栅电流是影响器件功耗及可靠性的重要因素之一,本文基于热载流子形成的物理过程,建立了单轴应变硅NMOSFET热载流子栅电流模型,并对热载流子栅电流与应力强度、沟道掺杂浓度、栅源电压、漏源电压等的关系,以及TDDB(经时击穿)寿命与栅源电压的关系进行了分析研究.结果表明,与体硅器件相比,单轴应变硅MOS器件不仅具有较小的热载流子栅电流,而且可靠性也获得提高.同时模型仿真结果与单轴应变硅NMOSFET的实验结果符合较好,验证了该模型的可行性.     

电离辐射对部分耗尽绝缘体上硅器件低频噪声特性的影响

本文针对辐射前后部分耗尽结构绝缘体上硅(SOI)器件的电学特性与低频噪声特性开展试验研究. 受辐射诱生埋氧化层固定电荷与界面态的影响, 当辐射总剂量达到1 M rad(Si) (1 rad = 10^-2 Gy)条件下, SOI器件背栅阈值电压从44.72 V 减小至12.88 V、表面电子有效迁移率从473.7 cm²/V·s降低至419.8 cm²/V· s、亚阈斜率从2.47 V/dec增加至3.93 V/dec; 基于辐射前后亚阈斜率及阈值电压的变化, 可提取得到辐射诱生界面态与氧化层固定电荷密度分别为5.33×10¹¹ cm^{- 2}与2.36×10¹² cm^-2. 受辐射在埋氧化层-硅界面处诱生边界陷阱、氧化层固定电荷与界面态的影响, 辐射后埋氧化层-硅界面处电子被陷阱俘获/释放的行为加剧, 造成SOI 器件背栅平带电压噪声功率谱密度由7×10^{- 10} V²·Hz^-1增加至1.8×10^-9 V² ·Hz^-1; 基于载流子数随机涨落模型可提取得到辐射前后SOI器件埋氧化层界面附近缺陷态密度之和约为1.42×10¹⁷ cm^-3·eV^-1和3.66×10¹⁷ cm^-3·eV^-1. 考虑隧穿削弱因子、隧穿距离与时间常数之间关系, 本文计算得到辐射前后埋氧化层内陷阱电荷密度随空间分布的变化.     

Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

Based on the quasi-two-dimensional(2D) solution of Poisson’s equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate(JLDMCSG) metal-oxide-semiconductor field-effect transistor(MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG(JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage rolloff of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional(3D) numerical device simulator ISE.     

SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting

In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved.     

Statistical emission of electrons from nanocrystalline silicon quantum dot memory nodes in a few-electron MOSFET memory device

Operation of a short and narrow channel metal-oxide-semiconductor field-effect transistor (MOSFET) memory device with a few nanocrystalline Si (nc-Si) dots in the active region has been investigated at 300 and 30 K. The discrete shift of the threshold voltage (V_th) in the current-voltage characteristics that arises from the screening effect of the charge stored in the nc-Si dot above the FET channel, suggests memory operation. It is found that the value of V_th changes with temperature whereas the magnitude of the shift in V_th is independent of temperature. The lifetime of the electrons stored in the floating node has also been investigated at different read voltages.     

总剂量辐照效应对窄沟道SOI NMOSFET器件的影响

本文深入研究了130 nm Silicon-on-Insulator (SOI) 技术下的窄沟道n型metal-oxide-semiconductor-field-effect-transistor (MOSFET) 器件的总剂量辐照效应. 在总剂量辐照下, 相比于宽沟道器件, 窄沟道器件的阈值电压漂移更为明显. 论文利用电荷守恒定律很好地解释了辐照增强的窄沟道效应. 另外, 本文首次发现, 对于工作在线性区的窄沟道器件, 辐照产生的浅沟槽隔离氧化物(STI) 陷阱正电荷会增加沟道区载流子之间的碰撞概率和沟道表面粗糙度散射, 从而导致主沟道晶体管的载流子迁移率退化以及跨导降低. 最后, 对辐照增强的窄沟效应以及迁移率退化进行了三维器件仿真模拟, 仿真结果与实验结果符合得很好. 关键词： 总剂量效应(TID) 浅沟槽隔离(STI) 氧化层陷阱正电荷 SOI MOSFET     

对称三材料双栅应变硅金属氧化物半导体场效应晶体管二维解析模型

提出了对称三材料双栅应变硅金属氧化物半导体场效应晶体管器件结构,为该器件结构建立了全耗尽条件下的表面势模型、表面场强和阈值电压解析模型,并分析了应变对表面势、表面场强和阈值电压的影响,讨论了三栅长度比率对阈值电压和漏致势垒降低效应的影响,对该结构器件与单材料双栅结构器件的性能进行了对比研究.结果表明,该结构能进一步提高载流子的输运速率,更好地抑制漏致势垒降低效应.适当优化三材料栅的栅长比率,可以增强器件对短沟道效应和漏致势垒降低效应的抑制能力.     

部分耗尽SOI MOSFET总剂量效应与偏置状态的关系

实验表明SOI MOSFET掩埋氧化层中的总剂量辐射效应与辐射过程中的偏置状态有关. 对诱发背沟道泄漏电流的陷阱电荷进行了研究. 建立一个数值模型来模拟不同偏置下陷进电荷的建立, 它包括辐射产生的载流子复合和俘获的过程. 模拟结果与实验结果相符, 解释了总剂量辐射效应受偏置状态影响的机理.     

Size and aerial density distributions of Ge nanocrystals in a SiO2 layer produced by molecular beam epitaxy and rapid thermal processing

We discuss the distribution of size and aerial density of Ge nanocrystals in a metal-oxide-semiconductor (MOS) memory structure fabricated by molecular beam epitaxy combined with rapid thermal processing; the size and aerial density of Ge nanocrystals are controlled by varying the thickness of the deposited Ge layer and the processing time. Variation of tunnel oxide thickness is demonstrated with the extension of the processing time. The effect of processing time and tunnel oxide thickness on the electrical properties of the MOS structures is investigated by high frequency capacitance–voltage measurements. PACS  61.46.+w; 81.07.-b; 81.07.Bc; 81.07.Ta     

一个非晶InGaZnO薄膜晶体管线性区陷阱态的提取方法

非晶InGaZnO(a-IGZO)薄膜在制备过程中形成的缺陷和弱键以陷阱态的形式非均匀分布在a-IGZO的带隙中, 这些陷阱态会俘获栅压诱导的电荷, 影响a-IGZO薄膜晶体管线性区迁移率、沟道电子浓度等, 进而影响线性区的电学性能. 本文基于线性区沟道迁移率与沟道内的自由电荷与总电荷的比值成正比, 分离出自由电荷以及陷阱态电荷. 由转移特性和电容电压特性得到自由电荷以及陷阱态电荷对表面势的微分, 分离出自由电子浓度和陷阱态浓度. 通过对沟道层与栅绝缘层界面运用泊松方程以及高斯定理, 考虑了沟道表面势与栅压的非均匀性关系, 得出自由电子浓度以及陷阱态浓度与表面势的关系, 最后通过陷阱态浓度与表面势求导得到线性区对应的态密度.     

界面态电荷对6H碳化硅N沟MOSFET阈值电压和跨导的影响

针对界面态密度在禁带中的不均匀分布,并且考虑到碳化硅材料中杂质的不完全离化,分析了界面态电荷对N沟6H碳化硅MOSFET阈值电压和跨导的影响.结果显示界面态密度的不均匀分布不仅使阈值电压增大,而且还会导致器件跨导变低,它是影响SiCMOSFET特性的一个重要因素 关键词： 碳化硅 界面态 阈值电压 跨导     

界面态电荷对n沟6H-SiC MOSFET场效应迁移率的影响

针对界面态密度在禁带中的不均匀分布，分析了界面态电荷对n沟6H碳化硅MOSFET场效应迁移率的影响.分析结果显示，界面态电荷使n沟碳化硅器件的场效应迁移率明显降低.并给出了实验测定的场效应迁移率和反型层载流子迁移率的比值与界面态密度之间关系. 关键词： 碳化硅 界面态 反型层迁移率 场效应迁移率