Barrier Enhancement Effect of Postannealing in Oxygen Ambient on Ni/AIGaN Schottky Contacts

Al0.2 Ga0.8N/GaN samples are grown by metalorganic chemical vapour deposition （MOCVD） method on （0001） sapphire substrates. A 10nm-thick Ni layer is deposited on AlGaN as the transparent Schottky contact. The effect of postannealing in oxygen ambient on the electrical properties of Ni/AlGaN is studied by current-voltage- temperature （I-V-T） measurement. The annealing at a relatively low temperature of 300℃ for 90 s results in a decrease of the ideality factor from 2.03 to 1.30 and an increase of the Schottky barrier height from 0.77eV to 0.954 e V. The I-V-T analysis confirms the improvement originated from the formation of NiO, a layer with higher resistance, which could passivate the surface states of AlGaN and suppress the tunnelling current. Furthermore, the annealing also leads to an increase of the transmittance of the contacts from 57.5% to 78.2%, which would be favourable for A1GaN-based photodetectors.     

Schottky barrier properties of various metal (Zr, Ti, Cr, Pt) contact on p-GaN revealed from I-V-T measurement

Schottky barrier contact using three different metal (Zr, Ti, Cr and Pt) and Ohmic contact using Ni were made on same epitaxial growth layer of p-GaN. Measurements were carried out using current-voltage-temperature (I-V-T) in the range of 27-100°C. Under forward bias and room-temperature (RT), the ideality factors (η) were determined to be 2.38, 1.82, 1.51 and 2.63, respectively, for Zr, Ti, Cr and Pt. The Schottky barrier height (SBH) and effective Richardson coefficient A^** were measured through modified Norde plot as one of the analysis tools. Barrier heights of 0.84, 0.82, 0.77 and 0.41 eV for Zr, Ti, Cr and Pt, respectively, were obtained from the modified Norde plot. Schottky barrier heights of Zr, Ti, or Cr/p-GaN were also measured through activation energy plot, and determined to be in the same range (∼0.87 eV) and Pt at 0.49 eV. These results indicate that the Fermi level seems to be pinned due to the value of slope parameter (S) was very low (S = −0.25).     

Evaluation of Schottky junction parameters from current-voltage characteristics exhibiting large excess currents

A new method is presented to extract the junction parameters from current-voltage characteristics of Schottky junctions exhibiting high leakage or other excess currents at low bias and current levels, for reduction of errors and uncertainity of the evaluation. In contrary to the Richardson plot, using the new method presented here, the Schottky junction parameters are evaluated from the measured experimental points directly instead of the extrapolated values of saturation current. The temperature dependence of forward bias, which is necessary for a given thermionic emission current level, is used. After transformation of the data, a linear plot is obtained, which yields both the barrier height and effective Richardson constant.     

Investigation on the barrier height and inhomogeneity of nickel silicide Schottky

The apparent Schottky barrier height (SBH) of the nickel silicide Schottky contacts annealed at different temperatures was investigated based on temperature dependence of I-V characteristic. Thermionic emission-diffusion (TED) theory, single Gaussian and double Gaussian models were employed to fit I-V experimental data. It is found the single Gaussian and double Gaussian SB distribution model can give a very good fit to the I-V characteristic of apparent SBH for different annealing temperatures. Also, the apparent SBH and the leakage current increase with annealing temperatures under reverse voltage. In addition, the homogeneity of interfaces for the samples annealed at temperatures of 500 and 600 °C is much better than that of the samples annealed at temperatures of 400, 700, and 800 °C. This may result from the phase transformation of nickel silicide due to the different annealing temperatures and from the low Schottky barrier (SB) patches.     

The barrier height inhomogeneity in Al/p-Si Schottky barrier diodes with native insulator layer

The current-voltage (I-V) characteristics of Al/p-Si Schottky barrier diodes (SBDs) with native insulator layer were measured in the temperature range of 150-375 K. The estimated zero-bias barrier height Φ_B0 and the ideality factor n assuming thermionic emission (TE) theory show strong temperature dependence. Evaluation of the forward I-V data reveals an increase of zero-bias barrier height Φ_B0 but decrease of ideality factor n with increase in temperature. The conventional Richardson plot exhibits non-linearity below 250 K with the linear portion corresponding to activation energy of 0.41 eV and Richardson constant (A^*) value of 1.3 × 10⁻⁴ A cm⁻² K⁻² is determined from intercept at the ordinate of this experimental plot, which is much lower than the known value of 32 A cm² K² for holes in p-type Si. Such behavior is attributed to Schottky barrier inhomogene ties by assuming a Gaussian distribution of barrier heights (BHs) due to barrier height inhomogeneities that prevail at interface. Also, Φ_B0 versus q/2kT plot was drawn to obtain evidence of a Gaussian distribution of the BHs, and values of Φ_B0 = 1.055 eV and σ₀ = 0.13 V for the mean BH and zero-bias standard deviation have been obtained from this plot, respectively. Thus, the modified versus q/kT plot gives Φ_B0 and A^* as 1.050 eV and 40.08 A cm⁻² K⁻², respectively, without using the temperature coefficient of the barrier height. This value of the Richardson constant 40.03 A cm⁻² K⁻² is very close to the theoretical value of 32 A K⁻² cm⁻² for p-type Si. Hence, it has been concluded that the temperature dependence of the forward I-V characteristics of the Al/p-Si Schottky barrier diodes with native insulator layer can be successfully explained on the basis of TE mechanism with a Gaussian distribution of the barrier heights.     

Schottky barrier and pn-junctionI/V plots — Small signal evaluation

This paper proposes and examines three different plots for the determination of the saturation current, the ideality factor, and the series resistance of Schottky diodes and solar cells from the measurement of a single current (I)/voltage(V) curve. All three plots utilize the small signal conductance and avoid the traditional Norde plot completely. A test reveals that the series resistance and the barrier height of a test diode can be determined with an accuracy of better than 1%. Finally it is shown that a numerical agreement between measured and fittedI/V curves is generally insufficient to prove the physical validity of current transport models.     

Current conduction mechanism in Al/p-Si Schottky barrier diodes with native insulator layer at low temperatures

The forward bias current-voltage (I-V) characteristics of Al/p-Si (MS) Schottky diodes with native insulator layer were measured in the temperature range of 80-300 K. The obtained zero bias barrier height Φ_B0(I-V), ideality factor (n) and series resistance (R_s) determined by using thermionic emission (TE) mechanism show strong temperature dependence. There is a linear correlation between the Φ_B0(I-V) and n because of the inhomogeneties in the barrier heights (BHs). Calculated values from temperature dependent I-V data reveal an unusual behaviour such that the Φ_B0 decreases, as the n and R_s values are increasing with decreasing absolute temperature, and these changes are more pronounced especially at low temperatures. Such temperature dependence of BH is contradictory with the reported negative temperature coefficient of the barrier height. In order to explain this behaviour we have reported a modification in the expression reverse saturation current I_o including the n and the tunnelling factor (αΧ^1/2δ) estimated to be 15.5. Therefore, corrected effective barrier height Φ_bef.(I-V) versus temperature has a negative temperature coefficients (α = −2.66 × 10⁻⁴ eV/K) and it is in good agreement with negative temperature coefficients (α = −4.73 × 10⁻⁴ eV/K) of Si band gap. In addition, the temperature dependent energy distribution of interface states density N_ss profiles was obtained from the forward bias I-V measurements by taking into account the bias dependence of the Φ_e and n. The forward bias I-V characteristics confirm that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that the current conduction mechanism of MS Schottky diodes.     

Correlation between barrier heights and ideality factors of Cd/n-Si and Cd/p-Si Schottky barrier diodes

Our goal is to experimentally investigate whether or not the effective Schottky barrier heights (SBHs) and ideality factors obtained from the current-voltage (I-V) and capacitance-voltage (C-V) characteristics differ from diode to diode even if the samples were identically prepared. For this purpose, we prepared Cd/n-Si (33 dots) and Cd/p-Si (15 dots) diodes. The SBH for the Cd/n-Si diodes ranged from 0.701 to 0.605 eV, and ideality factor n from 1.913 to 1.213. Φ_b value for the Cd/p-Si diodes ranged from 0.688 to 0.730 eV, and ideality factor n value from 1.473 to 1.040. The experimental SBH distributions obtained from the C⁻²-V and I-V characteristics were fitted by a Gaussian function and their mean SBH values were calculated. Furthermore, the laterally homogeneous barrier heights were also computed from the extrapolation of the linear plot of experimental barrier heights versus ideality factors.     

Effects of chemical treatment on barrier height and ideality factors of Au/GaN Schottky diodes

We have studied Au/n-GaN Schottky barrier diodes. GaN surfaces have been prepared by cleaning in HCl and (NH₄)₂S prior to metal deposition. The zero-biased barrier heights and ideality factors obtained from the current-voltage characteristics differ from diode to diode, although all the samples were prepared identically. The statistical analysis for the reverse bias C-V data yielded mean value of (1.35±0.04) eV for Schottky barrier height of HCl treated sample and (1.20±0.03) eV for (NH₄)₂S sample, where 9 dots were considered from each cleaning method. It was found that the barrier height values obtained from the C⁻²-V (1.43 eV) and I-V characteristics (0.89 eV) are different from each other by 0.54 eV. The inhomogeneous barrier heights were found to be related to the effect of the high series resistance on diode parameters (Akkiliç et al., 2004) [1].     

Intersecting behaviour of nanoscale Schottky diodes I-V curves

We describe a new feature connected with Schottky barriers with nanosize dimensions. We found out by theoretical analysis that the I-V curves of such small diodes measured at different temperatures should intersect and consecutively at higher voltages larger current flows through the diode at lower temperatures. This effect which is at first glance in contradiction with the thermionic theory is caused by the series resistance influence. We show that the presence of the series resistance is a necessary condition of its observation. However, the intersection voltage—minimum voltage at which the intersection may occur—increases with the value of the series resistance and the diode dimensions for which the effect could be observable in Si diodes and the common series resistance values must be in submicrometer range. Diodes with several hundreds nanometers dimension have the intersection voltage ∼1 V. Analytical expression for the intersection voltage values was also derived.     

Temperature dependence of the current-voltage characteristics of the Al/Rhodamine-101/p-Si(1 0 0) contacts

The current-voltage (I-V) characteristics of Al/Rhodamine-101/p-Si/Al contacts have been measured at temperatures ranging from 280 to 400 K at 20 K intervals. A barrier height (BH) value of 0.817 eV for the Al/Rh101/p-Si/Al contact was obtained at the room temperature that is significantly larger than the value of 0.58 eV of the conventional Al/p-Si Schottky diode. While the barrier height Φ_b0 decreases the ideality factors (n) become larger with lowering temperature. The high values of n depending on the sample temperature may be ascribed to decrease of the exponentially increase rate in current due to space-charge injection into Rh101 thin film at higher voltage. Therefore, at all temperatures, it has been seen that the I-V characteristics show three different regions, the ohmic behavior at low voltages, and the space charge limited current with an exponential distribution of traps at high voltages.     

Fermi Level Unpinning and Schottky Barrier Modification by Ti, Sc and V Incorporation at NiSi2/Si Interface

A new method is proposed to modify the Schottky barrier height （SBH） for nickel silicide/Si contact. Chemical and electrical properties for NiSi2/Si interface with titanium, scandium and vanadium incorporation are investigated by first-principles calculations. The metal/semiconductor interface states within the gap region are greatly decreased, which is related to the diminutions of junction leakage when Ti-cap is experimentally used in nickel silicide/Si contact process. It leads to an unpinning metal/semiconductor interface. The SBH obeys the Schottky-Mort theory. Compared to Ti substitution, the SBH for electrons is reduced for scandium and increases for vanadium.     

Influence of the interface structure on the barrier height of homogeneous Schottky contacts

Unreconstructed interfaces may be prepared by evaporation of thick Pb films onto surfaces at room temperature. Current-voltage and capacitance-voltage characteristics of such Schottky contacts were measured in the temperature range between 140 and 300 K. The experimental data are analyzed by applying the thermionic-emission theory of inhomogeneous metal-semiconductor contacts as well as the “standard” thermionic-emission theory. From both methods the Schottky barrier height of laterally homogeneous contacts results as 0.724 eV. This value is by 74 meV larger than the previously observed barrier heights of laterally homogeneous interfaces. Similar differences were reported for unreconstructed and reconstructed Al- and contacts. The reduced barrier heights of all these interfaces are explained by the electric dipole associated with the stacking faults of reconstructions at surfaces and interfaces. Received: 14 May 1998 /Revised and Accepted: 7 September 1998     

Influence of surface cleaning effects on properties of Schottky diodes on 4H-SiC

Ir/4H-SiC and IrO₂/4H-SiC Schottky diodes are reported in terms of different methods of surface pretreatment before contact deposition. In order to find the effect of surface preparation processes on Schottky characteristics the SiC wafers were respectively cleaned using the following processes: (1) RCA method followed by buffered HF dip. Next, the surface was oxidized (5.5 nm oxide) using a rapid thermal processing reactor chamber and circular geometry windows were opened in the oxide layer before metallization deposition; (2) the same as sequence (1) but with an additional in situ sputter etching step before metallization deposition; (3) cleaning in organic solvents followed by buffered HF dip. The I-V characteristics of Schottky diodes were analyzed to find a correlation between extracted parameters and surface treatment. The best results were obtained for the sequence (1) taking into account theoretical value of Schottky barrier height. The contacts showed excellent Schottky behavior with ideality factors below 1.08 and barrier heights of 1.46 eV and 1.64 eV for Ir and IrO₂, respectively. Very promising results were obtained for samples prepared using the sequence (2) taking into account the total static power losses because the modified surface preparation results in a decrease in the forward voltage drop and reverse leakage current simultaneously. The contacts with ideality factor below 1.09 and barrier height of 1.02 eV were fabricated for Ir/4H-SiC diodes in sequence (2).     

A unified model for metal/organic interfaces: IDIS, ‘pillow’ effect and molecular permanent dipoles

A unified model, embodying the induced density of interface states (IDIS) model, the reduction of the metal work function due to the adsorbed molecules (‘pillow’ effect) and molecular permanent dipoles, is presented for describing the barrier formation at metal/organic interfaces. While the IDIS model and ‘pillow’ effect have been described in previous approaches, in this paper we show how to introduce molecular permanent dipoles in the interface barrier formation. Examples for Au or Al/organic interfaces are discussed, which show the validity of our results and the generality of our formalism.     

Electrical Characteristics of Co/n-Si Schottky Barrier Diodes Using I-V and C-V Measurements

Electrical characteristics of Co/n-Si Schottky barrier diodes are analysed by current- voltage （I- V） and capacitancevoltage （C- V） techniques at room temperature. The electronic parameters such as ideality factor, barrier height and average series resistance are determined. The barrier height 0. 76 eV obtained from the C - V measurements is higher than that of the value 0. 70 eV obtained from the I - V measurements. The series resistance Rs and the ideality factor n are determined from the d ln（ I） /dV plot and are found to be 193.62 Ω and 1.34, respectively. The barrier height and the Rs value are calculated from the H（I） - I plot and are found to be 0.71 eV and 205.95Ω. Furthermore, the energy distribution of the interface state density is determined from the forward bias I - V characteristics by taking into account the bias dependence of the effective barrier height. The interface state density Nss ranges from 6.484×10^11 cm^-2eV^-1 in （Ec - 0.446） eV to 2.801×10^10 cm^-2eV^-1 in （Ec - 0.631） eV, of the Co/n-Si Schottky barrier diode. The results show the presence of a thin interracial layer between the metal and the semiconductor.     

The effect of interface states, excess capacitance and series resistance in the Al/SiO2/p-Si Schottky diodes

The current-voltage (I-V) characteristics of Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO₂ interface. The density of interface states (N_ss) distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) at room temperature for the Schottky diode on the order of ≅4 × 10¹³ eV⁻¹ cm⁻²_. These high values of N_ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The N_ss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V, C-V and G-V characteristics of SD are affected not only in N_ss but also in series resistance (R_s), and the location of N_ss and R_s has a significant on electrical characteristics of Schottky diodes.     

Nonideality of Au/Si and Au/GaAs Schottky barriers due to process-induced defects

A mechanism of local lowering of the Schottky barrier height (SBH) is proposed, which causes nonideality in nearly ideal Au/n-Si and Au/n-GaAs Schottky barriers. Positively ionized defects generated by the process very close to the interface induce electrons in the metal-induced gap states (MIGS) and lower the SBH locally. The spatial density distribution of the ionized defects obtained from the SBH distribution is determined by the unique interaction with the MIGS. The defects are considered to have the negative-U property and are neutralized at very close positions to the MIGS. The potential distributions close to the interface have a considerable potential drop due to the large defect density. These inhomogeneous potentials are coincident with the energy level scheme of the defect identified as the defect causing the nonideality. This defect is Si self-interstitial in Au/Si SB, and As antisite in Au/n-GaAs SB. This MIGS with process-induced defect model supersedes the previously proposed two major Fermi level pinning models. The mystery of the T₀ effect is solved. The thermionic-field emission current taking place in the strong electric field has influence on the I-V characteristics at low temperatures. Regarding the C-V characteristics of Au/Si SB, the observed extra capacitance under the forward bias is an experimental evidence in accordance with the proposed model.     

Observation of strain relaxation in Si1-xGex layers by optical and electrical characterisation of a Schottky junction

We have studied the effect of the strain relaxation on the band-edge alignments in a Pt/p-Si_1-xGe_x Schottky junction with x=0.14 by internal photoemission spectroscopy and current–voltage measurements. We have shown that the variations in the band-edge alignments can be observed directly by measuring the optical and electrical properties of a simple Schottky junction. The strain in the Si_1-xGe_x layer has been partially relaxed by thermal treatments at two different temperatures. The degree of relaxation and other structural changes have been determined by a high-resolution X-ray diffractometer. Both optical and electrical techniques have shown that the barrier height of the Pt/Si_0.86Ge_0.14 junction increases with the amount of relaxation in the Si_1-xGe_x layer. This shows that the valence-band edge of the Si_1-xGe_x layer moves away from the Fermi level of the Pt/Si_1-xGe_x junction. The band-edge movement results from the increase in the band gap of the Si_1-xGe_x layer after the strain relaxation. This result agrees with the theoretical predictions for the strain-induced effects on the Si_1-xGe_x band structure. Received: 18 October 2000 / Accepted: 19 December 2000 / Published online: 23 March 2001     

The effect of series resistance on capacitance-voltage characteristics of Schottky barrier diodes

The capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the Ti/p-Si Schottky barrier diodes (SBDs) have been investigated taking into account the effect of the interface states and series resistance of the device. The forward C-V measurements have been carried out in the range frequency of 0.3-2 MHz (at six different frequencies). It is seen that the forward C-V plots exhibit anomalous peaks in the presence of a series resistance. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. In addition to, the effect of series resistance on the capacitance is found appreciable at higher frequencies due to the capacitance decreases with increasing frequency.