A 533-MHz BiCMOS superscalar RISC microprocessor

This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm×10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5-μm BiCMOS process and requires 3.6 and 2.1 V power supplies     

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 μm, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1×, 2×, 3×, and 4× are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers     

A 180 MHz 0.8 μm BiCMOS modular memory family of DRAM andmultiport SRAM

A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM     

A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbidetector for disk drive read channels

An architecture for efficiently implementing linear and nonlinear Viterbi detectors for magnetic read channels is presented. By employing generalized noiseless target values for the Viterbi trellis, the detector is better able to adapt to the actual binary data storage channel and less equalization is needed, resulting in a significant reduction in the probability of error. An implementation example is presented for the case of a 16-state Viterbi detector having a capability of handling any noiseless target of up to five adjacent nonzero values. In a 0.6 μm (drawn) 3.0 V CMOS process, the design has been implemented with a die area of 9 mm² consuming under 350 mW of power when operated at 110 MHz     

A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocelllibrary

A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm² die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz     

350 MHz opamp-RC filter in 0.18 μm CMOS

A 350 MHz fifth-order elliptic opamp-RC filter demonstrates that opamp-based filters need not have bandwidth disadvantages compared to transconductor-based filters. The filter, fabricated in standard digital 0.18 μm CMOS with 1.8 V V_DD, achieves 0.5 Vp-p signal swing at -40 dB THD     

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design     

A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

A 300 MHz digital double-sideband to single-sideband converter in 1μm CMOS

A 43-tap FIR Hilbert transform digital filter chip is described which implements both a double-sideband (DSB) to single-sideband (SSB) conversion with a decimation-by-2 and the converse operation of a SSB to DSB conversion with an interpolation-by-2. Over 70 dB of image rejection is achieved by the Hilbert transform filter. The 3.57×7.07 mm², 45 000 transistor chip was fabricated in a 1 μm N-well CMOS process and operates at sample rates in excess of 300 MHz     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage     

A 3-V 5.4-mW BiCMOS track & hold circuit with samplingfrequency up to 150 MHz

A track & hold circuit to be used in front of a high-speed analog-to-digital converter (ADC) is proposed. In order to achieve the required resolution with a single 3-V supply, a fully differential closed-loop architecture is used. The track & hold circuit processes a differential 1-Vpp output signal swing and achieves more than 8-b linearity with sampling frequency up to 150 MHz. In these conditions, the total power consumption is 5.4 mW from a single 3-V supply. The circuit has been realized in a 0.7 μm BiCMOS technology, and its active area is about 0.15 mm²     

GaInAsSb-AlGaAsSb tapered lasers emitting at 2.05 μm with 0.6-Wdiffraction-limited power

Tapered lasers fabricated from a GaInAsSb-AlGaAsSb single-quantum-well structure are reported. The laser structure, grown by molecular beam epitaxy, has broad-stripe pulsed threshold current densities as low as 50 A/cm² at room temperature. Tapered lasers have exhibited diffraction-limited continuous-wave output power up to 600 mW     

A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150Ms/s sampling frequency

In order to increase the sampling frequency of SC filters the Precise Opamp Gain (POG) design approach is presented. It is based on the use of large bandwidth opamps with low but precise DC gain. The finite gain value is taken into account in the design phase. This produces capacitor values slightly different from those obtained with the standard design. A BiCMOS opamp with a nominal gain of 96 and unity-gain frequency of 650 MHz is used in a biquadratic lowpass filter with Q=2.8 designed with the POG approach. In a 1.2 μm BiCMOS technology, the prototype lowpass biquad operates with sampling frequency up to 150 Ms/s with 0.2 dB accuracy in the transfer function. For a sampling frequency of 150 Ms/s, the cut off frequency is 15 MHz. The dynamic range (for 1% THD) is 67 dB, and THD is less than -60 dB for a 1.5 Vpp 5 MHz input signal. The chip area is 1 mm², and the power consumption is 20 mW     

A low-noise-figure 1.5 μm multiple-quantum-well opticalamplifier

The authors report on the noise characteristics of InGaAs/InGaAsP multiple-quantum-well optical amplifiers operating near 1.5 μm. A noise figure of 4.4 dB is reported, verifying the predicted low-noise properties of quantum-well amplifiers     

Parametric oscillation at 3.2 μm in KTP pumped at 1.064 μm

The author reports the stable generation of 0.2-W average power IR pulses around 3.2 μm from the KTP parametric oscillator pumped by the Nd:YAG laser at 1.064 μm. In addition, improved Sellmeier's equations, which correctly predict almost all of the nonlinear experiments thus far reported, are presented, together with the absolute values of d₃₁ and d₃₂     

Multipass diode-pumped Nd:YAG optical amplifiers at 1.06 μm and1.32 μm

We have built two versions of a diode-pumped Nd:YAG amplifier using a compact multipass confocal geometry with a fiber-coupled input. This confocal geometry provided efficient power and high gain in a volume of approximately 100 cm³. When pumped with a commercially mature 2 W 809 nm laser diode, the 1.06 μm version produced 460 mW and a small signal gain of 51 dB. The 1.32 μm version produced 170 mW and a small signal gain of 29 dB. Such an efficient amplifier, especially at 1.32 μm would be useful as a power booster in fiber optic telecommunications     

Refractive index and material dispersion interpolation of dopedsilica in the 0.6-1.8 μm wavelength region

An extension of the Claussius-Mossotti interpolation scheme is proposed so that the refractive index and material dispersion of GeO₂- and F-doped silica glasses (with doping concentrations different than those of published data) can be predicted in the 0.6-1.8-μm wavelength region. The new interpolation expression provides a well-behaved functional relationship for use in computer models which analyse propagation in single-mode fibers. The technique proposed is particularly powerful because it can be applied to any glass, whether single or multicomponent, having any other single dopant     

A 2-μm BiCMOS process utilizing selective epitaxy

A 2-μm BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2-μm CMOS process with a poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors