GGMOS型静电放电防护器件的高功率微波效应北大核心CSCD

采用基于半导体漂移扩散模型的数值模拟软件对高功率微波(HPM)作用下GGMOS型的静电放电(ESD)防护器件效应进行了数值模拟研究。对ESD器件在HPM作用下的响应特性及器件内部的物理图像进行了数值模拟。数值模拟的结果表明,外部注入HPM信号的幅值和频率是影响ESD器件的因素,在加载30ns脉宽的HPM脉冲作用下,器件内部达到的最高温度与信号幅值成正指数关系。在给ESD注入相同幅值的HPM信号时,频率越大,器件达到失效温度所需要的时间越长。     

短沟道金属-氧化物半导体场效应晶体管的散粒噪声模型

随着金属-氧化物半导体场效应晶体管(MOSFET)器件的尺寸进入到纳米量级,器件的噪声机理逐渐开始转变.传统的热噪声与漏源电流模型精度出现下降,散粒噪声成为器件噪声不可忽略的因素.本文通过求解能量平衡方程,推导了短沟道MOSFET器件的沟道电子温度和电子速度表达式,由此建立了漏源电流模型;基于漏源电流模型建立了适用于40 nm以下器件的散粒噪声模型和热噪声模型.研究了n型金属-氧化物半导体场效应晶体管(NMOSFET)器件在不同偏置电压下,器件尺寸对散粒噪声抑制因子和噪声机理的影响.研究表明:已有的热噪声模型与散粒噪声模型的精度随着器件尺寸的减小而下降,导致相应的散粒噪声抑制因子被高估.当NMOSFET器件的尺寸减小到10 nm时,器件的噪声需由热噪声与受抑制的散粒噪声共同表征.本文建立的短沟道器件散粒噪声模型可应用于纳米尺寸NMOSFET器件噪声性能的分析与建模.     

SiC肖特基源漏MOSFET的阈值电压

SiC肖特基源漏MOSFET的阈值电压不同于传统的MOSFET的阈值电压.在深入分析工作机理的基础上,利用二维模拟软件ISE提取并分析了器件的阈值电压.对SiC肖特基源漏MOSFET的阈值电压给出物理描述,得出当源极载流子主要以场发射方式进入沟道,同时沟道进入强反型状态,此时的栅电压是该器件的阈值电压. 关键词： 碳化硅 肖特基接触 阈值电压     

高电子迁移率晶体管微波损伤仿真与实验研究

针对AlGaAs/InGaAs型高电子迁移率晶体管,利用TCAD半导体仿真工具,从器件内部空间电荷密度、电场强度、电流密度和温度分布变化分析出发,研究了从栅极注入1 GHz微波信号时器件内部的损伤过程与机理。研究表明,器件的损伤过程发生在微波信号的正半周,负半周器件处于截止状态;器件内部损伤过程与机理在不同幅值的注入微波信号下是不同的。当注入微波信号幅值较低时,器件内部峰值温度出现在栅极下方靠源极侧栅极与InGaAs沟道间,由于升温时间占整个周期的比例太小,峰值温度很难达到GaAs的熔点;但器件内部雪崩击穿产生的栅极电流比小信号下栅极泄漏电流高4个量级,栅极条在如此大的电流下很容易烧毁熔断。当注入微波信号幅值较高时,在信号正半周的下降阶段,在栅极中间偏漏极下方发生二次击穿,栅极电流出现双峰现象,器件内部峰值温度转移到栅极中间偏漏极下方,峰值温度超过GaAs熔点。利用扫描电子显微镜对微波损伤的高电子迁移率晶体管器件进行表面形貌失效分析,仿真和实验结果符合较好。     

高迁移率In0.6Ga0.4As沟道MOSHEMT与MOSFET器件特性的研究

从模拟和实验两个方面对高迁移率In_0.6Ga_0.4As沟道金属氧化物半导体高电子迁移率晶体管（MOSHEMT）和金属氧化物半导体场效应晶体管（MOSFET）器件开展研究工作.研宄发现InAlAs势垒层对Ino_0.6Ga_0.4AsMOSHEMT的特性具有重要影响.与Ino_0.6Ga_0.4As MOSFET相比,Ino_0.6Ga_0.4As MOSHEMT表现出优异的电学特性.实验结果表明,In_0.6Ga_0.4As MOSHEMT的有效沟道迁移率达到2812 cm²/V.s^-1,是In_0.6Ga_0.4As MOSFET的3.2倍.0.02 mm栅长的MOSHEMT器件较相同栅长的MOSFET器件具有更高的驱动电流、更大的跨导峰值、更大的开关比、更高的击穿电压和更小的亚阈值摆幅.     

高电子迁移率晶体管放大器高功率微波损伤机理

在TCAD半导体仿真环境中,建立了0.25 m栅长的AlGaAs/InGaAs高电子迁移率晶体管(HEMT)低噪声放大器与微波脉冲作用的仿真模型,基于器件内部的电场强度、电流密度和温度分布的变化,研究了1 GHz的微波从栅极和漏极注入的损伤机理。研究结果表明,从栅极注入约40.1 dBm的微波时,HEMT内部峰值温度随着时间的变化振荡上升,最终使得器件失效,栅下靠源侧电流通道和强电场的同时存在使得该位置最容易损伤;从漏极注入微波时,注入功率的高低会使器件内部出现不同的响应过程,注入功率存在一个临界值,高于该值,器件有可能在第一个周期内损伤,损伤位置均在漏极附近。在1 GHz的微波作用下,漏极注入比栅极注入更难损伤。     

一个圆柱形双栅场效应晶体管的物理模型

圆柱形双栅场效应晶体管(CSDG MOSFET)是在围栅MOSFET器件增加内部控制栅而形成,与双栅、三栅及围栅MOSFET器件相比,圆柱形双栅MOSFET提供了更好的栅控性能和输出特性.本文通过求解圆柱坐标系下的二维泊松方程,得到了圆柱形双栅MOSFET的电势模型;进一步对反型电荷沿沟道积分,建立其漏源电流模型.分析讨论了圆柱形双栅MOSFET器件的电学特性,结果表明:圆柱形双栅MOSFET外栅沿沟道的最小表面势和器件的阈值电压随栅介质层介电常数的增大而减小,其漏源电流和跨导随栅介质层介电常数的增大而增大;随着器件参数的等比例缩小,沟道反型电荷密度减小,其漏源电流和跨导也减小.     

高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

基于流体动力学模型的2维砷化镓金属半导体场效应管数值模拟

 介绍了用于描述工作在高频强电场条件下的亚微米半导体器件的流体动力学模型，并讨论了为求解流体动力学模型所采用的算子分裂方法和有限体积法。使用流体动力学模型，对亚微米GaAs金属半导体场效应管器件进行了2维数值模拟，得到了该器件的I-V曲线、电子密度分布和电子温度分布。数值模拟结果表明，器件栅极电压越负，肖特基结的耗尽层越厚，源漏电流越小；在耗尽层内电场最强处，电子温度达到4 000 K;在强电场下，电子温度将严重偏离晶格温度，形成所谓热电子。     

Channel length effect in a MOSFET structure by scanning capacitance microscopy

Depth dependent carrier density and trapped charges in a metal-oxide-semiconductor field effect transistor (MOSFET) like structure have been studied using scanning capacitance microscopy (SCM). For a MOSFET structure, since minority carrier can be provided by the source and drain diffusions, its response time is shorter than that of metal-oxide-semiconductor (MOS) system. So the high frequency C-V relation is slightly different from that of MOS capacitor and shows the characteristics dependent on the channel length. Bias dependent SCM images which represent the depth dependent carrier density and detrapping time constant of trapped charges in the oxide layer were observed to see the channel effect in a MOSFET structure.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

环栅肖特基势垒金属氧化物半导体场效应管漏致势垒降低效应研究

结合环栅肖特基势垒金属氧化物半导体场效应管(MOSFET)结构, 通过求解圆柱坐标系下的二维泊松方程得到了表面势分布, 并据此建立了适用于低漏电压下的环栅肖特基势垒NMOSFET阈值电压模型.根据计算结果, 分析了漏电压、沟道半径和沟道长度对阈值电压和漏致势垒降低的影响, 对环栅肖特基势垒MOSFET器件以及电路设计具有一定的参考价值. 关键词： 环栅肖特基势垒金属氧化物半导体场效应管 二维泊松方程 阈值电压模型 漏致势垒降低     

The pulsed microwave damage trend of a bipolar transistor as a function of pulse parameters

In the present paper we conduct a theoretical study of the thermal accumulation effect of a typical bipolar transistor caused by high power pulsed microwaves(HPMs),and investigate the thermal accumulation effect as a function of pulse repetition frequency(PRF) and duty cycle.A study of the damage mechanism of the device is carried out from the variation analysis of the distribution of the electric field and the current density.The result shows that the accumulation temperature increases with PRF increasing and the threshold for the transistor is about 2 kHz.The response of the peak temperature induced by the injected single pulses indicates that the falling time is much longer than the rising time.Adopting the fitting method,the relationship between the peak temperature and the time during the rising edge and that between the peak temperature and the time during the falling edge are obtained.Moreover,the accumulation temperature decreases with duty cycle increasing for a certain mean power.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.     

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal-oxide-semiconductor field-effect transistor(MOSFET)under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation.The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track.The time for energy deposition in SiC is on the order of picoseconds.The TCAD is used to simulate the single event burnout(SEB)sensitivity of SiC MOSFET at four representative incident positions and four incident depths.When heavy ions strike vertically from SiC MOSFET source electrode,the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer,strike from the channel,and strike from the body diode region.High current and strong electric field simultaneously appear in the local area of SiC MOSFET,resulting in excessive power dissipation,further leading to excessive high lattice temperature.The gate-source junction area and the substrate-epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature.In the SEB simulation of SiC MOSFET at different incident depths,when the incident depth does not exceed the device's epitaxial layer,the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.     

基于有限元方法的有机场效应晶体管特性模拟与实验验证

采用有限元方法,借助多物理场软件COMSOL模拟了底栅顶接触结构有机场效应晶体管电位和载流子浓度随源漏电压Vds的变化。模拟结果表明,当固定栅压V_g=-10 V时,改变V_(ds)从0~-10 V,对于电位分布,从栅极到源漏电极竖直方向有渐进的变化,而从源极到漏极的水平方向呈现由大到小明显的梯度变化。对于载流子浓度,观察到沟道处从源极向漏极逐渐减少,在靠近漏极的区域减少得尤为明显,而当源漏电压等于栅极电压时,产生夹断现象。进一步将模拟结果与实际制备的器件性能进行了对比,模拟结果与实验数据所显示的分布趋势大体相同,印证了模拟的合理性。由此表明,采用模拟方法分析有机场效应晶体管的器件特性,对于实际制备器件具有重要的指导意义。