CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

Photoresponse analysis and pixel shape optimization for CMOS active pixel sensors

In this work, a semi-analytical model, based on a thorough analysis of experimental data, is developed for photoresponse estimation of a photodiode-based CMOS active pixel sensor (APS). The model covers the substrate diffusion effect together with the influence of the photodiode active-area geometrical shape and size. It describes the pixel response dependence on integration photocarriers and conversion gain and demonstrates that the tradeoff between these two conflicting factors gives an optimum geometry enabling extraction of maximum photoresponse. The parameter dependence on the process and design data and the degree of accuracy for the photoresponse modeling are discussed. Comparison of the derived expression with the measurement results obtained from a 256/spl times/256 CMOS APS image sensor fabricated via HP in a standard 0.5-/spl mu/m CMOS process exhibits excellent agreement. The simplicity and the accuracy of the model make it a suitable candidate for implementation in photoresponse simulation of CMOS photodiode arrays.     

Transversal-readout architecture for CMOS active pixel image sensors

Novel architecture for CMOS active pixel image sensors (APSs), which eliminates the vertically striped fixed pattern noise (FPN), is presented. There are two kinds of FPN for CMOS APSs. One originates from the pixel-to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and column-reset transistor, a source-follower input transistor, and a column-select transistor instead of the row-select transistor found in conventional CMOS APSs. The column-select transistor is connected to a signal line that runs horizontally instead of vertically. An experimentally fabricated 320/spl times/240-pixel CMOS APS employing the transversal-readout architecture exhibited neither vertically nor horizontally striped FPN. A buried-photodiode device with the transversal-readout architecture is also proposed.     

Readout circuit for CMOS active pixel image sensor

The design and simulation results of a new readout circuit for a CMOS active pixel image sensor are presented. This scheme removes the fixed pattern noise and reduces the signal degradation while offering an increase in readout speed, compared with the conventional approach     

A CMOS image sensor with a double-junction active pixel

A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters.     

CMOS active pixel image sensors for highly integrated imagingsystems

A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-μm CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 μm×40 μm with 26% fill-factor. Array sizes of 28×28 elements and 128×128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 μV/e^- for the p-well devices and 6.5 μV/e^- for the n-well devices. Input referred read noise of 28 e^- rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed     

Passivation issues in active pixel CMOS image sensors

Most of the integrated circuit industry follows a final passivation process which consists of a low temperature passivation layer deposition and a thermal anneal. This two step process is particularly relevant in CMOS imagers where the dark current is a major issue. This work shows that passivation material plays an important role in the device performance. We measured H diffusion through the final silicon nitride layer and we compare these results with the material properties and passivation efficiency.     

Dual-mode wide dynamic range CMOS active pixel sensor

A new dual-mode wide dynamic range CMOS image sensor is designed, which is capable of two different operating modes: logarithmic and floating point mode. The proposed sensor can choose the operating mode manually or adaptively. A prototype pixel is designed and tested with standard 0.5 /spl mu/m CMOS process.     

Layout techniques for radiation hardening of standard CMOS active pixel sensors

This article presents a radiation hardened active pixel sensor implemented in a standard 0.35 μm CMOS process. The integrated circuit is composed of a 64 × 64 pixel matrix with a 25 μm pixel pitch and has four different pixel architectures. There are also test structures to permit the characterization of the MOS transistors. The radiation hardening of the circuit is implemented with two layout techniques: enclosed geometry transistors and guard rings. It is shown that, with these techniques, the sensor is able to operate with total ionization doses that surpass 500 krad, which is more than double of the requirement for our application. Also, the techniques do not compromise the optical response of the pixels. To obtain an electrical model of the designed transistors, an EKV MOSFET Model was extracted.     

A CMOS AC/DC charge pump for a wireless sensor network

实现了一种应用于无线网络传感器的基于MOS管的AC/DC电荷泵,提出的AC/DC电荷泵在0.13μm公益平台实现能够提供稳定的工作电压,同时具有低功耗及高充电效率。电荷泵采用了具有低阈值（Vth）的MOSFET二极管,提高了转换效率。给出了电压倍增器的模型,仿真结果和芯片测试结果。     

A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design

In this paper, a new design of on-chip CMOS voltage regulator, which provides two stable power supplies to charge pump and voltage controlled oscillator (VCO) in charge pump phase-locked loop (PLL), is presented. A power supply noise rejection (PSNR) whose peaking is less than −40 dB is achieved over the entire frequency spectrum for VCO supply. The voltage regulator provides maximum 14 mA current, and static current is about 780 μA at 3.3 V. Based on the proposed voltage regulator, a PLL clock generator has been developed and measured in the AMS 0.35 μm CMOS process. Operating at 160 MHz, a period jitter of 13.64 ps was measured under a clean power supply, while period jitter became 16.24 ps under a power supply modulated with a 400 mV, 10 kHz square wave.     

CMOS active pixel sensor star tracker with regional electronicshutter

A 64×64 element CMOS active pixel sensor (APS) for star tracker applications is reported. The chip features an innovative regional electronic shutter through the use of an individual pixel reset architecture. Using the regional electronic shutter, each star in the field of view can have its own integration period. This way, simultaneous capture of bright stars with dim stars is accommodated, enabling a large increase in tracker capability. The chip achieves 80 dB dynamic range, 50 e-rms read noise, low dark current, and excellent electronic shutter linearity     

A low voltage hybrid bulk/SOI CMOS active pixel image sensor

A hybrid bulk/silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) active pixel image sensor has been fabricated and studied. The active pixel comprised of reset and source follow transistors on the SOI thin film while the photodiode is fabricated on the SOI handling substrate after removing the buried oxide. The bulk photodiode can be optimized for efficiency with the use of lightly doped SOI substrate without compromising the circuit performance. On the other hand, the elimination of wells on the SOI thin-film allows the use of PMOSFET without increasing the pixel size. The addition of a PMOSFET in the active pixel structure can reduce the minimum operating voltage of the circuit beyond that of conventional designs. With the combination of the high quantum efficiency of bulk photodiode and the low power advantage of SOI technology, the hybrid technology is attractive for scaled low voltage imaging applications     

CMOS active pixel image sensor with simple floating gate pixels

A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It features complete reset that results in no kTC noise and no image lag, high blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 32(H)×27(V) pixel area array. Since the pixel structure is relatively simple, small pixel size is feasible     

A CMOS active pixel sensor based DNA micro-array with nano-metallic particles detection protocol

A DNA micro-array (DMA) for DNA detection is reported. The DMA combines a standard CMOS active pixel image sensor with a DNA detection protocol utilizing the binding of DNA targets and probes functionalized with gold nano-particles that can modify the opaqueness at the detection site. The DMA has been fabricated using a 0.5 μm CMOS process together with on-chip timing control and correlated double sampling. Experimental results show that the system can detect DNA samples with extremely low concentration down to 10 pM using ordinary light source.     

Object location and centroiding techniques with CMOS active pixel sensors

A system based on a pixel-parallel CMOS active pixel sensor architecture is demonstrated for capturing the location and approximate size of an object. The object is distinguished from the background by a global threshold. Three prototype sensors are implemented in standard CMOS technologies. In the first, a high fill factor three-transistor pixel with integral comparator is demonstrated. It is shown that performance of this sensor is limited by device nonuniformities, so a novel in-pixel fixed-pattern noise correction circuit using a single capacitor is demonstrated in the second sensor. The system concept is further enhanced by a cumulative cross section readout architecture which provides additional information regarding the object with little reduction in speed. The application of these systems to centroid determination using multiple thresholds is discussed.     

Analysis of temporal noise in CMOS photodiode active pixel sensor

Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise     

CMOS有源光电传感器像素采集单元成像质量分析

针对CMOS光电二极管型有源像素采集单元中存在的拖影问题,从像素采集单元的工作原理入手,利用光电二极管的等效电路模型,对像素采集单元的光电转换状态和置位状态进行分析.得出造成拖影的根本原因是光电二极管置位后的电压与上一周期末光电二极管的光生电压有关.     

A multi-mode low ripple charge pump with active regulation

In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented.The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6-μm-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10-30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.