A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 E_k, 1 E_k and 1.5 E_k tunneling energy levels, respectively when compared with the previous most power-efficient design.

     

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

     

An Efficient Module for Full Adders in Quantum-dot Cellular Automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work.     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

A Cost-Aware Efficient RAM Structure Based on Quantum-Dot Cellular Automata Nanotechnology

Nowadays quantum-dot cellular automata (QCA) as a nanoscale transistor-less device technology have attained major attention for their prominent features. The circuits constructed by QCA technology owning remarkable decreasing in size, fast switching speed and ultra-low energy consumption. These features can be more different in varied memory structures. Random access memory (RAM) is a kind of data storage devices that allows data to be read or written it’s generally volatile, and used for data that change often. Due to the significance of memory in a digital system, designing and optimization of high-speed RAM in QCA nanotechnology is a substantial subject. So, this paper presents a new structure for QCA-based RAM cell by employing the 3-input rotated majority gate (RMG). Eventually, 1 × 4 RAM is designed by exerting the individual memory cell. The functionality of the proposed design is implemented and assessed using the QCADesigner simulator. The obtained results demonstrated that the designed QCA-based RAM cell is superior to previous structures in terms of delay and cell count.

     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

Design of Novel Coplanar Counter Circuit in Quantum Dot Cellular Automata Technology

One of the emerging technology that can be used for replacing CMOS technology is Quantum-dot Cellular Automata (QCA) technology. Counter circuits are widely used circuits in the design of digital circuits. This paper presents and evaluates circuits for 2-, 3-, 4-, and 5-bit coplanar counter in the QCA technology. The designed QCA coplanar counter circuits are based on the modified D-Flip-Flop (D-FF) circuit that is designed in this paper. The designed QCA circuits are implemented and verified by using QCADesigner tool version 2.0.3. The results show that the designed circuits for 2-, 3-, 4-, and 5-bit coplanar counter contain 44 (0.03 μm²), 93 (0.07 μm²), 160 (0.13 μm²), and 245 (0.2 μm²) quantum cells (area). The comparison results indicate that the designed circuits have advantages compared to other QCA circuits in terms of cost, area, and cell count.

     

基于概率模型的量子元胞自动机加法器容错性能研究

采用概率转移矩阵方法和电路分割理论建立了两种结构的量子元胞自动机 (QCA)加法器的容错性模型, 深入分析了各组成元件对加法器的整体容错性能的影响. 指出元件在较低的正确概率时, 传输线对整体正确概率影响较小, 而当元件正确概率较高时, 传输线的正确概率对整体正确概率的影响急剧增大, 并且在整个参数变化范围内反相器始终是影响整体正确概率的主要元件. 采用Frobenius范数对两种同一功能不同结构的QCA加法器的整体容错性能进行了比较, 发现由5输入择多逻辑门构成的QCA加法器的整体容错性能优良. 这对于目前QCA加法器的容错性设计以及今后大规模QCA电路的容错性设计具有重要意义.     

A new double negative metamaterial for multi-band microwave applications

This paper reveals the design and analysis of a new split-H-shaped metamaterial unit cell structure that is applicable for multi-band frequency range, and it shows negative permeability and permittivity at those frequency bands. In the basic design, the two separate split square resonators have been added by a metal link to form H-shape unit structure. Moreover, the analyses and comparison of the 1 × 1-array, 2 × 2-array structures and 1 × 1, 2 × 2 unit cell configurations have been investigated. All these configurations demonstrate its multi-band operating frequency (S-band, C-band, X-band, K _u -band) with double negative characteristics. The equivalent circuit model for the unit cell is presented to demonstrate the validation of the resonant behavior. The commercially available finite-difference time-domain based simulation software CST microwave studio has been used to get the reflection and transmission parameters of the unit cell. In summation, the material also exhibits single negative characteristics in the multi-band frequency range if it is projected on the 20 × 20 mm² substrates. The simplicity, scalability, double negative characteristics, and multi-band operations have made this design novel in the electromagnetic paradigm.     

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.     

Quantum legitimacy of reversible gate and a new design of multiplier based on R gate

Quantum full adders play a key role in the design of quantum computers. The efficiency of a quantum adder directly determines the speed of the quantum computer, and its complexity is closely related to the difficulty and the cost of building a quantum computer. The existed full adder based on R gate is a great design but it is not suitable to construct a quantum multiplier. We show the quantum legitimacy of some common reversible gates, then use R gate to propose a new design of a quantum full adder. We utilize the new designed quantum full adder to optimize the quantum multiplier which is based on R gate. It is shown that the new designed one can be optimized by a local optimization rule so that it will have lower quantum cost than before.     

Towards Multilayer QCA SISO Shift Register Based on Efficient D-FF Circuits

Quantum-dot Cellular Automata (QCA) is a new technology for replacing CMOS technology at nano-scale dimansion. Shift registers have commonly used circuit in the digital circuits design. In this paper, a new 3-bit Serial Input-Serial Output (SISO) QCA shift register is presented. The proposed circuit uses 3 novel D-Flip-Flops (D-FFs) that are developed in this paper. The proposed circuits are implemented by using QCADesigner tool version 2.0.3. The developed QCA SISO shift register has 120 cells and 0.03 μm² area. The results show that the developed circuits have advantages compared to other QCA circuits in terms of area.     

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

     

RETRACTED ARTICLE: A New Design of 2-Bit Universal Shift Register Using Rotated Majority Gate Based on Quantum-Dot Cellular Automata Technology

Quantum-dot Cellular Automata (QCA) is emerging nanotechnology that can represent binary information using quantum cells without current flows. It is known as a promising alternative of Complementary Metal–Oxide Semiconductor (CMOS) to solve its drawbacks. On the other hand, the shift register is one of the most widely used practical devices in digital systems. Also, QCA has the potential to achieve attractive features than transistor-based technology. However, very small-scale and Nano-fabrication limits impose a hurdle to the design of QCA-based circuits and necessitate for fault-tolerant analysis is appeared. Therefore, the aim of this paper is to design and simulate an optimized a D-flip-flop (as the main element of the shift register) based on QCA technology, which is extended to design an optimized 2-bit universal shift register. This paper evaluates the performance of the designed shift register in the presence of the QCA fault. Collected results using QCADesigner tool demonstrate the fault-tolerant feature of the proposed design with minimum clocking and area consumption.

     

A NEW CMOS READOUT CIRCUIT FOR VO2-BASED UNCOOLED FOCAL PLANE ARRAYS

A new CMOS readout circuit for VO₂-based uncooled FPAs is presented in this paper. The on-chip readout circuit consists of three major parts: An input circuit of BCDI structure, a column-shared integration circuit of CTIA structure, and a common CDS output circuit. The simple configuration of the input circuit makes it possible to operate more circuits in parallel, and increases the integration time and number of pixels, the column-shared integration circuit which is suitable for small pixel size provides low noise, high gain, a highly stable detector bias, and high photon current injection efficiency, and the common CDS output circuit is utilized to reduce or eliminate low-frequency noise of the readout circuit. An experimental readout chip for 50-μm-pitch 32×32 element VO₂-based uncooled FPAs has been fabricated. The measurement results of the fabricated readout chip have successfully verified its readout function and excellent performance.     

Novel Efficient Circuit Design for Multilayer QCA RCA

The novel emerging technology, QCA technology, is a candidate for replacing CMOS technology. Full Adder (FA) circuits are also widely used circuits in arithmetic circuits design. In this paper, two new multilayer QCA architectures are presented: one-bit FA and 4-bit Ripple Carry Adder (RCA). The designed one-bit multilayer FA architecture is based on a new XOR gate architecture. The designed 4-bit multilayer QCA RCA is also developed based on the designed one-bit multilayer QCA FA. The functionality of the designed architectures are verified using QCADesigner tool. The results indicate that the designed architecture for 4-bit multilayer QCA RCA requires 5 clock phases, 125 QCA cells, and 0.17 μm² area. The comparison results confirm that the designed architectures provide improvements compared with other adder architectures in terms of cost, cell count, and area.

     

A Surface Mounting Embedded Optical Transceiver with Bi-Directional Data Rate of Eight Channels × 10 Gbps

Abstract

The bi-directional data rate is investigated of an eight-channel × 10-Gbps optical transceiver with a size of 15 mm × 15 mm × 6 mm and ball grid array package form that was designed and fabricated. A passive optical coupling method is designed based on a coupling lens array, which is transformed to substrate through a carrier. This electrical performance is characterized through a 3D full wave simulation and shows great advantages compared with traditional pluggable optical transceivers. Experimental eye diagram measurement in loop-back mode via a 2-m-long multi-mode fiber array shows an eye width of 51.984 ps at a bit-error rate order of 10^?12, which proves the transceiver's ability for 10.3125-Gbps data transmission.     

Design of Improved Arithmetic Logic Unit in Quantum-Dot Cellular Automata

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.