一种超高频宽带RFID标签天线

文章提出了一种弯折偶极子和T型匹配构成的RFID(Radio Frequency ID entification)标签天线。对称的弯折偶极子可以有效地产生全向方向图,T型匹配电路则可以灵活地调整输入阻抗使得标签芯片在较宽的带宽内实现阻抗的共扼匹配。该天线理论最大可读取距离达10.4m,根据具体应用该天线也可牺牲读取距离来减小尺寸。其带宽可覆盖全球RFID超高频范围(840～956MHz)。     

新型偶极子UHFRFID标签天线的设计

采用大共面偶极子和悬浮贴片,并嵌入缝隙来实现共轭匹配,设计了一款覆盖了UHFRFID系统应用的所有频段的新型标签天线。该天线通过调节缝隙的大小来调节与标签芯片阻抗的匹配,该天线尺寸为70mm×40mm×1．6mm．S11〈-15dB的带宽为776．991MHZ,增益为1．11dB。仿真结果表明,该天线满足工程上的应用。     

RFID标签天线的研究现状及热点问题探讨

本文从介绍RFID系统的基本原理开始,分析了RFID标签天线对于整个RFID系统的重要性,总结了RFID标签天线的设计要求以及近期国内外对各类别标签天线的研究状况,根据其设计原理提出改进思想,最后探讨并分析了近期标签天线的设计热点.     

一种应用于RFID 的印刷倒F 天线设计

基于平面倒F 天线模型,设计了一种用于2.4GHz RFID 系统的印刷倒F 单极子天线。采用易于射频集成的微带馈电方式,并结合带线阻抗变换,以实现较宽的阻抗带宽;采用在印刷倒F 结构正上方加载寄生辐射贴片,以提高天线增益。利用高频电磁仿真软件Ansoft HFSS 对提出的天线进行了建模、仿真和优化设计,该天线在2.28-2.51GHz 频率 范围内VSWR＜2,达到了10%左右的阻抗带宽,特别在RFID 系统的工作频段内（2.401GHz~2.409GHz）VSWR＜1.35, 增益＞2.36dBi。该天线具有尺寸小,重量轻,成本低等众多优点,能应用于工作于2.4GHz 的各种RFID 系统中。     

UHF频段RFID标签天线的小型化设计

提出了一种UHF频段的小型化标签天线,采用紧凑的弯折偶极子形式,通过附加一种新的T型阻抗匹配环结构,得到了非常好的阻抗匹配效果。针对Alien Higgs2型标签芯片,芯片的阻抗为7.4-j113Ω,天线在915 MHz工作频率下的输入阻抗为7.40Ω+112.98Ω,两者实现了较好的共轭匹配。天线整体平面尺寸为20 mm×60 mm,比常见的弯折偶极子结构标签天线的尺寸缩减了25%。天线的S11<-3 dB的工作频段为884 MHz到958 MHz,覆盖了74%的UHF频段,最大增益为0.94dBi。结果表明该天线具有良好的辐射性能,具有低损耗、小型化的优点。     

一种新型的hilbert分形rfid标签天线

随着射频识别技术研究的迅速发展,寻求具有尺寸缩减特性的天线结构成为RFID设计的实际需要,Hilbert分形结构是天线小型化设计的一种有效解决方案.本文论述了Hilbert分形天线的基本原理,对弯折偶极子天线采用Hilbea分形结构进行小型化设计,并对实物进行仿真.经测试与仿真后结果表明:标签天线尺寸约为25.6mm*16.2mm,工作在中心频率915MHz处,增益达到2.19dB,相对阻抗带宽为90MHz.天线能保持较好的工作性能,可应用于酒瓶盖防伪RFID标签中.     

一种宽频带UHF RFID标签天线的研究与设计

文章以宽频带UHF RFID标签天线的设计为研究对象,设计并仿真了一款工作在920MHz的电子标签天线。天线的尺寸为80mm 44mm,在反射系数-24dB的带宽可达160MHz,方向性比较好。同时标签天线结构简单,采用的制作材料也很大降低了其生产成本。     

应用于矿井的RFID应答器设计

采用RFID(射频识别)芯片IA4420设计了一款主动式应答器,主要应用于矿井安全生产管理。其工作中心频率为905 MHz,数据通信的核心部分是印刷偶极子天线,从仿真结果来看:其相对带宽约为40%,增益约为4.236 dB,输入阻抗接近纯电阻50Ω,性能参数较好。     

RFID标签天线测试架设计

针对RFID标签天线性能参数测试困难的问题,提出了平面结构的天线测试架的构想,设计并制作了一个实际的测试架.测试架包括平衡/不平衡转换器和阻抗匹配网络两部分,仿真和实验结果吻合得很好,能够实现对弯折线偶极子标签天线的输入阻抗、方向图和增益等参数准确的测量,并为其他小型平衡馈电天线的测试提供了参考.     

一种应用于金属表面的准八木标签天线

本文研究设计了一种应用于金属物体表面的高增益RFID标签天线。采用八木天线的理论,在天线上方增加网状结构的金属层,引导天线所辐射的电磁波尽量向标签上方传播,减少贴附到金属表面时产生的不利影响。天线增益达到5.5dBi,读写距离达到8.5m。     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

一种饱和功率为21dBm，峰值效率为35%的应用于900MHz RFID阅读器的CMOS线性功率放大器

本文在CMOS 0.18μm Mixed Signal工艺上实现了工作于900MHz的两级差分线性功率放大器,该功放工作于class AB状态。本文探讨了低压下输出匹配和谐波抑制网络,以提高功放的输出功率及效率,降低输出谐波。测试结果表明,在1.8V的电源电压下,功放在900MHz频率的输出饱和功率达到21.1dBm,输出1dB压缩点的功率为18.4dBm,峰值功率增加效率为35.4%,功率增益为23.3dB,各谐波分量也得到很好的控制。两级功放加上PAD的芯片总面积为1.2×0.55mm2。通过单芯片测试以及基于原型机的测试结果表明,该功放可以满足UHF RFID阅读器的应用。     

A compact low-power UHF RFID tag

In this paper, the design of an ultra-low-power UHF RFID tag is introduced. The system architecture and the communication protocols are chosen to operate with the minimum requirements possible from the RFID tag. By moving most of system functionality to the RFID reader side, the circuit requirements of the RFID tag circuits are relaxed. Supply voltages for both analog and digital parts are chosen carefully for minimum power consumption. The RFID tag is designed in standard digital 0.13 μm CMOS technology. Simulations results of the main blocks are shown. The power consumption of the chip is only 1 μW, and the chip area is only 0.14 mm×0.23 mm.     

High-efficiency dynamic supply CMOS audio power amplifier for low-power applications

This paper describes the analysis and design of a dynamic supply CMOS audio power amplifier for low-power applications. The dynamic supply technique is used to increase the efficiency of a class AB power amplifier. The polarization of its output stage is adaptive so that the maximum efficiency enhancement can be achieved without jeopardizing the linearity of the system. Two types of adaptive polarization are proposed and compared. A concept of power supplies switching is also proposed. Simulation results are presented showing that an efficiency of 53.6% at a total harmonic distortion (THD) of less than 0.1% can be achieved, whereas the maximal theoretical value for a class AB amplifier is approximately 33.3%.     

A low power CMOS compatible embedded EEPROM for passive RFID tag

A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18 μm CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018 mm² and consumes 14.5 and 370 μW for read and write at 85 °C, respectively.     

A digitally controlled power amplifier with neutralization capacitors for Zigbee~(TM) applications

正This paper presents a single chip CMOS power amplifier with neutralization capacitors for Zigbee~(TM) system according to IEEE 802.15.4.A novel structure with digital interface is adopted,which allows the output power of a PA to be controlled by baseband signal directly,so there is no need for DAC.The neutralization capacitors will increase reverse isolation.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed power amplifier has a 13.5 dB power gain,3.48 dBm output power and 35.1%PAE at P_(1dB) point. The core area is 0.73×0.55 mm~2.     

应用于Zigbee通信协议的采用了中和技术的数字控制功率放大器

本文介绍了一种CMOS全片集成的功率放大器,满足802.15.4规范,并采用采用了中和电容技术。采用了一种新型的采用了数字接口的结构,可以使基带信号直接控制PA的输出功率,从而无需DAC。采用中和电容技术以提高反向隔离度。该芯片采用SMIC 0.18um工艺流片。 测试结果表明,在1dB压缩点处,本文所提出的功率放大器具有13.5dB的功率增益,最大3.48dBm的输出功率和35.1%的PAE。核心面积为0.73mm*0.55mm。