Design of a low power video decompression chip set for portable applications

This paper describes the design process of a chip set which performs real-time video decompression for wireless portable applications and concentrates on four critical aspects of the design: compression algorithm development, control complexity, programmability, and throughput. For each of these design areas, this paper evaluates the design trade-offs between low power, compression efficiency, and throughput, which are the three main requirements for wireless portable video. The chip set consists of a subband reconstruction chip and a pyramid vector quantization (PVQ) decoder chip and requires no external memory support or frame buffer. For portable applications with a resolution of 176 pixels wide, 240 lines, and 30 frames per second color video, the chip set, operating at a 1.35 V supply, dissipates less than 9 mW.This research was supported by JSEP contract number DAAH04-94-G-0058.     

Partitioned state encoding for low power in FPGAs

The problem of finite state machine (FSM) encoding for low power in field-programmable gate arrays (FPGAs) is addressed. In this technology, one-hot encoding is typically recommended for large FSMs and binary encoding for small FSMs. A partitioned encoding approach is proposed which uses a combination of both binary encoding and zero-one-hot encoding with intermediate code size. Experimental results demonstrate that the proposed encoding approach can produce significant power savings.     

Measurement of low impedance on chip power supply loop

A new method of measuring the high frequency self-impedance and transfer impedance of a microprocessor's power supply loop is proposed. The method is based on measurement of the on-chip voltage in response to a predetermined stimulus. Two methods of the stimulus current generation are presented: running a set of computer instructions and toggling clock frequency while the system is in reset.     

无线传感器网络的智能低功耗侦听协议

无线传感器网络MAC层协议低功耗侦听(LPL)使用较长的前导码,在密集部署的无线传感器网络中造成较大的"串音"开销.提出一种智能低功耗侦听协议(SLPL),通过在前导码中嵌入目的地址和前导码长度索引,能有效降低非目的节点的串音开销,减少目的节点的接收开销.理论分析和部署测试表明SLPL的能效比LPL有显著提高,同时测试显示SLPL功耗小于X-MAC协议.     

Network on a chip: modeling wireless networks with asynchronousVLSI

We introduce the notion of a network on a chip: a programmable asynchronous VLSI architecture for fast and efficient simulation of wireless networks. The approach is inspired by the remarkable similarity between networks and asynchronous VLSI. Our approach results in simulators that can evaluate network scenarios much faster than real time, enabling a new class of network protocols that can dynamically change their behavior based on feedback from in situ simulation. We describe our simulation architecture, and present results that validate our approach     

Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs

Software implementation costs of most algorithms, designed for image compression in wireless sensor networks, do not justify their use to reduce the energy consumption and delay transmission of images. Even though the hardware solution looks to be very attractive for this problem, a specific care should be paid when designing a low power algorithm for image compression and transmission over these systems. The aim of this paper is to present and evaluate a hardware implementation for user-driven image compression scheme designed to respect the energy constraints of image transmission over wireless sensor networks (WSNs). The proposed encoder will be considered as a co-processor for tasks related with image compression and data packetization. In this paper, we discuss both of the hardware architecture and the features of this encoder circuit when prototyped on FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) circuits.     

基于SOI的低功耗智能卡芯片技术

利用SIMOX材料制作智能卡是一种新的技术.本文简要介绍了智能卡的发展及应用,描述了利用SOI(SIMOX)技术制作的新型智能卡芯片,概述了其优点,并分析了现存的问题.     

A Ka-band low power consumption MMIC core chip for T/R modules

This paper presents a Ka-band low power consumption MMIC core chip using commercial 0.15 μm D-mode GaAs pHEMT technology for T/R modules. The core chip consists of two linear gain amplifiers, a SPDT switch, a 5-bit attenuator and a 5-bit phase shifter with a size of 4.8 mm × 2.5 mm. In the receiving mode, the 32–38 GHz core chip results in a gain of 9.0 dB and an output P_1dB of –3 dBm. In the transmitting mode, the gain and output P_1dB are 11.5 dB and +0 dBm, respectively. The measured rms attenuation error and phase error are 0.7 dB and 3.8°. The power consumption is 150 mW in both work modes. The measured results show that the operating bandwidth, power consumption, gain, rms attenuation error and phase error have been significantly improved compared with the previous reports.     

应用于UHF RFID标签的低功耗真随机数发生器

设计了一种基于振荡采样法的真随机数发生器.针对UHF RFID标签芯片功耗低、面积小的特点,利用简单有效的电路结构增强发生器的随机性.采用频率受控的被采样数据振荡器与采样时钟异或后形成初步随机数,并增加异或链输出负反馈结构,有效提高了输出序列中"0""1"分布的均匀性,降低了序列的自相关性.标签采用SMIC 0.18μm RF CMOS工艺设计并流片,采样时钟为2MHz,总工作电流少于2μA.     

Bufferless broadcasting: a low power distributed circuit techniquefor broadcasting 10-Gb/s chip input signals

Bufferless distributed circuit (BDC) broadcasting is proposed as a technique for broadcasting high-speed chip input signals to a series of on-chip destination cells as needed in crosspoint switch, parallel multiplier, distributed amplifier, etc., chip designs. In contrast with conventional techniques that use an on-chip buffer to assist broadcasting, BDC broadcasting offers the advantage of lower signal delay and power dissipation. In an experimental GaAs heterojunction bipolar transistor (HBT) 8×4 crosspoint switch assembly, BDC broadcasting was found to achieve a 40% power savings with little or no penalty in jitter or bit error rate performance at a 10-Gb/s data rate     

Magnetics on silicon: an enabling technology for power supply on chip

Data from the ITRS2003 roadmap for 2010 predicts voltages for microprocessors in hand-held electronics will decrease to 0.8V with current and power increasing to 4A and 3W, respectively. Consequently, low power converters will move to multimegahertz frequencies with a resulting reduction in capacitor and inductor values by factors of 5 and 20, respectively. Values required at 10 MHz, for a low power buck converter, are estimated at 130 nH and 0.6 uF, compatible with the integration of magnetics onto silicon and the concept of power supply-on-chip (PSOC). A review of magnetics-on-silicon shows that inductance values of 20 to 40nH/mm/sup 2/ can be achieved for winding resistances less than 1/spl Omega/. A 1-/spl mu/H inductance can be achieved at 5 MHz with dc resistance of 1/spl Omega/ and a Q of four. Thin film magnetic materials, compatible with semiconductor processing, offer power loss density that is lower than ferrite by a factor of 5 at 10 MHz. Other data reported includes, lowest dc resistance values of 120 m/spl Omega/ for an inductance of 120 nH; highest Q of 15 for an inductance of 350 nH and a current of 1 A for a 1- /spl mu/H inductor. Future technology challenges include reducing losses using high resistivity, laminated magnetic materials, and increasing current carrying capability using high aspect-ratio, electroplated copper conductors. Compatible technologies are available in the power switch, control, and packaging space. Integrated capacitor technology is still a long-term challenge with maximum reported values of 400 nF/cm/sup 2/.     

适用于片内集成的可修调低失调LDO

提出了一种新型可修调低失调LDO电路,该电路适于片内集成应用.现有的修调方法一般直接作用在反馈网络中,修调电路的自身失调会造成修调精度损失.本文提出一种失调隔离模块,以大大减小修调电路引入的误差.仿真结果表明,在修调电路发生10％的电流失调时,输出电压仅变化0.31％,使LDO输出电压的修调获得很好的线性度.     

Centralized congestion control routing protocol based on multi-metrics for low power and lossy networks

Owing to the unreliability of wireless link and the resource constraints of embedded devices in terms of energy, processing power, and memory size in low power and lossy networks (LLNs), network congestion may occur in an emergency and lead to significant packet loss and end-to-end delay. To mitigate the effect of network congestion, this paper proposes a centralized congestion control routing protocol based on multi-metrics (CCRPM). It combines the residual energy of a node, buffer occupancy rate, wireless link quality, and the current number of sub-nodes for the candidate parent to reduce the probability of network congestion in the process of network construction. In addition, it adopts a centralized way to determine whether the sub-nodes of the congested node need to be switched based on the traffic analysis when network congestion occurs. Theoretical analysis and extensive simulation results show that compared with the existing routing protocol, the performance of CCRPM is improved significantly in reducing the probability of network congestion, prolonging average network lifetime, increasing network throughput, and decreasing end-to-end delay.     

A mathematical framework for effective routing over low power and lossy networks

With the rapid advancement in the Internet of things, protocols are challenged to perform routing with low power over lossy networks (RPLs). Performance analysis of RPL attracted many researchers in the field. However, to the best of our knowledge, limited or no studies have been made to develop heterogeneous analytical models that aim at the classification and ranking of RPL deployments based on combinations of desired properties. In this paper, we develop an analytical framework that captures the effectiveness of RPL and enables its sound evaluation and classification. Performance metrics include power consumption, churn in, received packets, and duty cycle, to name but a few. The obtained results based on our analytical framework confirms its effectiveness compared to the simulation results obtained in the literature. The best performance is noted for the deployments with 50 m of range and for different number of nodes.     

一种防止信息丢失的双光路假彩色编码方法

本文提出一种利用正、负编码片和双光路技术获得全信息假彩色图像的新方法.文中论述了用这种方法不但能解决原编码方法可能修丢失信息的不足,又能对原方法不宜处理的高反差黑白片进行假彩色化处理的原理;给出了处理医用X光片的实验结果和照片.     

Minimum cost load balanced multipath routing protocol for low power and lossy networks

Conventional shortest path routing mechanisms in low power and lossy networks (LLNs) impose excessive traffic load on some nodes and cause their early battery depletion. Load balancing via multipath routing is a promising solution to increase lifetime. This idea is practised by some algorithms, mostly through limited number of disjoint paths, to reduce inter-path interference. In this paper a proactive multipath routing algorithm called MRPL is proposed, based on the recent standard routing protocol for LLNs. The algorithm tries to distribute the traffic load through a set of braided paths, with the objective of maximizing the network lifetime and minimizing total transmission cost. The traffic distribution mechanism is formulated by a linear program and a heuristic method is proposed to implement it in a distributed manner. Simulation results provide enough evidence for energy and cost efficiency of the proposed routing mechanism.     

基于MSP430单片机的低功耗LED点阵显示屏设计

文章介绍了基于MSP430单片机的低功耗LED点阵汉字显示屏的设计。本设计采用MSP430F249作为主控芯片,74HC系列154和595芯片构成行列驱动电路,4个16×16LED点阵级联构成16×64点阵显示器。该设计能够实现LED点阵显示器的汉字滚动循环显示,具有设计简单、显示清晰、超低功耗等特点。     

Comparing application layer protocols for video transmission in IoT low power lossy networks: an analytic comparison

Wireless Networks - Wide-spread use of low power lossy networks (LLNs) in internet of things (IoT) raises numerous challenges to video transmission over those networks. Deployment of proper...     

Single chip controller for a high-switching frequency DC/AC power inverter

The design and implementation of a new controller for a DC/AC power inverter is described. The controller uses the high switching frequency sinusoidal PWM technique and achieves excellent output voltage regulation, frequency stability and dynamic response in a noiseless, light-weight and cost-effective construction. The inverter performance is analysed using experimental results as well as the harmonic analysis based on the generalized piecewise linear waveform representation. As these results indicate, most of the output power is concentrated on the fundamental harmonic component making the method suitable for use in driving inductive loads in various applications, such as photovoltaic systems.