不同样式的高功率微波对双极晶体管的损伤效应和机理

结合Si基n⁺-p-n-n⁺ 外延平面双极晶体管, 通过分析器件内部的温度分布变化以及电流密度和烧毁时间随信号幅值的变化关系, 研究了其在三角波信号、正弦波信号和方波脉冲信号等三种样式的高功率微波信号作用下的损伤效应和机理. 研究表明, 三种高功率微波信号注入下器件的损伤部位都是发射结, 在频率和信号幅值相同的情况下方波脉冲信号更容易使器件损伤; 位移电流密度和烧毁时间随信号幅值的增大而增大, 而位移电流在总电流所占的比例随信号幅值的增大而减小; 相比于因信号变化率而引起的位移电流, 信号注入功率在高幅值信号注入损伤过程中占主要作用. 利用数据分析软件, 分别得到了三种信号作用下器件烧毁时间和信号频率的变化关系式. 结果表明, 器件烧毁时间随信号频率的增加而增加, 烧毁时间和频率都符合t= af^b的关系式. 关键词： 双极晶体管 高功率微波 损伤机理 信号样式     

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop(TFS) superjunction(SJ) insulated gate bipolar transistor(IGBT) with a buried oxide(BO) layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT(Conv-SJ), the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop(Vce(on)) and an improved tradeoff between Vce(on)and turn-off loss(Eoff), with no breakdown voltage(BV) degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5 μm and Nn = Np = 3 × 1015cm-3, the Vce(on)and Eoffof the proposed structure are 1.08 V and 2.81 mJ/cm2with the collector doping concentration Nc = 1×1018cm-3and 1.12 V and1.73 mJ/cm2with Nc = 5 × 1017cm-3, respectively. However, with the same device parameters, the Vce(on)and Eofffor the Conv-SJ are 1.81 V and 2.88 mJ/cm2with Nc = 1 × 1018cm-3and 1.98 V and 2.82 mJ/cm2with Nc = 5 × 1017cm-3,respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.     

Non-recessed-gate quasi-E-mode double heterojunction AIGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction A1GaN/GaN high electron mobility transistor （quasi-E- DHEMT） with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering （DIBL） was presented. Due to the metal organic chemical vapor deposition （MOCVD） grown 9-nm undoped A1GaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas （2DEG） was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1%tm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm. The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of -6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

超结硅锗碳异质结双极晶体管机理研究与特性分析优化

提出一种超结硅锗碳异质结双极晶体管(SiGeC HBT)新结构.详细分析了新结构中SiGeC基区和超结结构的引入对器件性能的影响,并对其电流输运机制进行研究.基于SiGeC/Si异质结技术,新结构器件的高频特性优良;同时超结结构的存在,在集电区内部水平方向和垂直方向都建立了电场,二维方向上的电场分布相互作用大大提高了新结构器件的耐压能力.结果表明:超结SiGeC HBT与普通结构SiGeC HBT相比,击穿电压提高了48.8%;更重要的是SiGeC HBT器件中超结结构的引入,不会改变器件高电流增益、高频率特性的优点;新结构器件与相同结构参数的Si双极晶体管相比,电流增益提高了10.7倍,截止频率和最高震荡频率也得到了大幅度改善,很好地实现了高电流增益、高频率特性和高击穿电压三者之间的折中.对超结区域的柱区层数和宽度进行优化设计,随着柱区层数的增多,击穿电压显著增大,电流增益有所提高,截止频率和最高震荡频率减低,但幅度很小.综合考虑认为超结区域采用pnpn四层结构是合理的.     

Influence of a two-dimensional electron gas on current—voltage characteristics of Al0.3{Ga}0.7 N/GaN high electron mobility transistors

The J-V characteristics of AltGa1 tN/GaN high electron mobility transistors（HEMTs） are investigated and simulated using the self-consistent solution of the Schro dinger and Poisson equations for a two-dimensional electron gas（2DEG） in a triangular potential well with the Al mole fraction t = 0.3 as an example.Using a simple analytical model,the electronic drift velocity in a 2DEG channel is obtained.It is found that the current density through the 2DEG channel is on the order of 10^13 A/m^2 within a very narrow region（about 5 nm）.For a current density of 7 × 10^13 A/m62 passing through the 2DEG channel with a 2DEG density of above 1.2 × 10^17 m^-2 under a drain voltage Vds = 1.5 V at room temperature,the barrier thickness Lb should be more than 10 nm and the gate bias must be higher than 2 V.     

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.     

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.     

High-efficiency S-band harmonic tuning GaN amplifier

In this paper, we present a high-efficiency S-band gallium nitride （GaN） power amplifier （PA）. This amplifier is fabri- cated based on a self-developed GaN high-electron-mobility transistor （HEMT） with 10 mm gate width on SiC substrate. Harmonic manipulation circuits are presented in the amplifier. The matching networks consist of microstrip lines and discrete components. Open-circuited stub lines in both input and output are used to tune the 2rid harmonic wave and match the GaN HEMT to the highest efficiency condition. The developed amplifier delivers an output power of 48.5 dBm （70 W） with a power-added efficiency （PAE） of 72.2% at 2 GHz in pulse condition. When operating at 1.8-2.2 GHz （20% relative bandwidth）, the amplifier provides an output power higher than 48 dBm （,-~ 65 W）, with a PAE over 70% and a power gain above 15 dB. When operating in continuous-wave （CW） operating conditions, the amplifier gives an output power over 46 dBm （40 W） with PAE beyond 60% over the whole operation frequency range.     

Evaluation of thermal resistance constitution for packaged A1GaN/GaN high electron mobility transistors by structure function method＊

The evaluation of thermal resistance constitution for packaged A1GaN/GaN high electron mobility transistor （HEMT） by structure function method is proposed in this paper. The evaluation is based on the transient heating measurement of the A1GaN/GaN HEMT by pulsed electrical temperature sensitive parameter method. The extracted chip-level and package-level thermal resistances of the packaged multi-finger A1GaN/GaN HEMT with 400μm SiC substrate are 22.5 K/W and 7.2 K/W respectively, which provides a non-invasive method to evaluate the chip-level thermal resistance of packaged A1GaN/GaN HEMTs. It is also experimentally proved that the extraction of the chip- level thermal resistance by this proposed method is not influenced by package form of the tested device and temperature boundary condition of measurement stage.     

高电子迁移率晶体管微波损伤仿真与实验研究

针对AlGaAs/InGaAs型高电子迁移率晶体管,利用TCAD半导体仿真工具,从器件内部空间电荷密度、电场强度、电流密度和温度分布变化分析出发,研究了从栅极注入1 GHz微波信号时器件内部的损伤过程与机理。研究表明,器件的损伤过程发生在微波信号的正半周,负半周器件处于截止状态;器件内部损伤过程与机理在不同幅值的注入微波信号下是不同的。当注入微波信号幅值较低时,器件内部峰值温度出现在栅极下方靠源极侧栅极与InGaAs沟道间,由于升温时间占整个周期的比例太小,峰值温度很难达到GaAs的熔点;但器件内部雪崩击穿产生的栅极电流比小信号下栅极泄漏电流高4个量级,栅极条在如此大的电流下很容易烧毁熔断。当注入微波信号幅值较高时,在信号正半周的下降阶段,在栅极中间偏漏极下方发生二次击穿,栅极电流出现双峰现象,器件内部峰值温度转移到栅极中间偏漏极下方,峰值温度超过GaAs熔点。利用扫描电子显微镜对微波损伤的高电子迁移率晶体管器件进行表面形貌失效分析,仿真和实验结果符合较好。     

Significant performance enhancement in A1GaN/GaN high electron mobility transistor by high-κ organic dielectric

The electrical properties of A1GaN/GaN high electron mobility transistor （HEMT） with and without high-κ organic dielectrics are investigated. The maximum drain current ID max and the maximum transconductance gm max of the organic dielectric/A1CaN/GaN structure can be enhanced by 74.5%, and 73.7% compared with those of the bare A1GaN/GaN HEMT, respectively. Both the threshold voltage VT and gm max of the dielectric/AlGaN/GaN HEMT are strongly dielectric-constant-dependent. Our results suggest that it is promising to significantly improve the performance of the A1GaN/GaN HEMT by introducing the high-κ organic dielectric.     

低温LBJT性能表征

作为集成电路的重要组成器件,双极结型晶体管在高速高频等方面有着互补金属氧化物半导体不能替代的优点.由于常规双极结型晶体管在低温环境中增益骤降,器件性能大幅衰减,故双极结型晶体管低温性能的研究较少且仅限于77K以上的温度.本文对在绝缘体上硅衬底上制造的与CMOS工艺相兼容的对称水平双极结型晶体管进行了4.2～300K宽温度范围的变温直流性能的测试,研究了施加正向衬底偏压对器件性能的影响,并探究了基于LBJT PN结的结温与温度关系用作低温温度传感器的可能性.通过施加12V的正向衬底偏压,得出了LBJT在4.2K的低温下具有～100的增益,并且LBJT PN结的正向电压与温度具有良好的线性关系,具备用作低温片上集成温度传感器的可能性.     

100-nm T-gate InAIAs/InGaAs InP-based HEMTs with fT= 249 GHz and fmax ： 415 GHz

InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain-gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 0.mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InA1As/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.     

Fabrication and characterization of 4H—SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H-SiC bipolar junction transistor with a double base epilayer that is continuously grown.The measured dc common-emitter current gain is 16.8 at IC = 28.6 mA(J C = 183.4 A/cm2),and it increases with the collector current density increasing.The specific on-state resistance(Rsp-on) is32.3mΩ·cm 2 and the open-base breakdown voltage reaches 410 V.The emitter N-type specific contact resistance and N + emitter layer sheet resistance are 1.7×10-3 Ω·cm2 and 150 /,respectively.     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal–oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.     

高功率微波作用下高电子迁移率晶体管的损伤机理

本文针对高电子迁移率晶体管在高功率微波注入条件下的损伤过程和机理进行了研究,借助SentaurusTCAD仿真软件建立了晶体管的二维电热模型,并仿真了高功率微波注入下的器件响应.探索了器件内部电流密度、电场强度、温度分布以及端电流随微波作用时间的变化规律.研究结果表明,当幅值为20 V,频率为14.9 GHz的微波信号由栅极注入后,器件正半周电流密度远大于负半周电流密度,而负半周电场强度高于正半周电场.在强电场和大电流的共同作用下,器件内部的升温过程同时发生在信号的正、负半周内.又因栅极下靠近源极侧既是电场最强处,也是电流最密集之处,使得温度峰值出现在该处.最后,对微波信号损伤的高电子迁移率晶体管进行表面形貌失效分析,表明仿真与实验结果符合良好.     

AlGaN/GaN高电子迁移率晶体管肖特基高温退火机理研究

在不同应力条件下,研究了AlGaN/GaN高电子迁移率晶体管高温退火前后的电流崩塌、栅泄漏电流以及击穿电压的变化.结果表明,AlGaN/GaN高电子迁移率晶体管通过肖特基高温退火以后,器件的特性得到很大的改善.利用电镜扫描(SEM)和X射线光电子能谱(XPS)对高温退火前、后的肖特基接触界面进行深入分析,发现器件经过高温退火后,Ni和AlGaN层之间介质的去除,并且AlGaN材料表面附近的陷阱减少,使得肖特基有效势垒提高,从而提高器件的电学特性. 关键词： AlGaN/GaN高电子迁移率晶体管 肖特基接触 界面陷阱     

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n~+-layer

A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.     

A novel structure of a high current gain 4H-SiC BJT with a buried layer in base

In this paper, a new structure of a 4H-SiC bipolar junction transistor (BJT) with a buried layer (BL) in the base is presented. The current gain shows an approximately 100% increase compared with that of the conventional structure. This is attributed to the creation of a built-in electric field for the minority carriers to transport in the base which is explained based on 2D device simulations. The optimized design of the buried layer region is also considered by numeric simulations.