Nickel silicide as a contact material for submicron CMOS devices

Nickel monosilicide (NiSi) is an attractive alternative to the currently used silicides for the coming generations of deep submicron complementary metaloxide-semiconductor (CMOS) devices. This silicide material has a resistivity, which is comparable to that of TiSi₂ or CoSi₂, but consumes less silicon for its formation. The silicide silicon interface is relatively planar and, unlike TiSi₂, its resistivity does not change with the linewidth for narrow lines. However, the thermal stability of NiSi is relatively poor at the currently used temperatures during process integration. Recent studies have shown that the stability of these films could be increased substantially through the small addition of alloy elements, which do not increase the resistivity of the NiSi film. Morever, it has been demonstrated that the addition of a small amount of alloy elements significantly reduces diode leakage, possibly due to the suppression of silicide spike formation as a result of alloy addition. This paper will present and discuss the details of these experimental results.     

两步镍硅化工艺及保护氮气的作用

A two-step process of Ni silicide formed on bulk silicon, and the effects of different process conditions, including two-step RTA temperature and time, selective etching, and process protective nitrogen gas on the properties of the Ni silicide film have been studied. In particular, the experiments show that the quality of NiSi film is very sensitive to the process conditions of the first RTA. The experiments also show that the quality of the film is very sensitive to the flow of protective nitrogen gas. The corresponding mechanisms are discussed.     

Two-step Ni silicide process and influence of protective N2 gas

e corresponding mechanisms are discussed.     

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co–Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co–Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni₂Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi₂ at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.     

A Hafnium interlayer method to improve the thermal stability of NiSi film

The effect of a thin Hafnium interlayer on the thermal stability of NiSi film has been investigated. Both X-ray diffraction and Raman spectra show that no high resistivity NiSi₂ appears in the Hf-additioned films which were post-annealed at temperatures ranging from 600 °C to 800 °C. Auger electron spectroscopy and Rutherford back scattering show that the Hf interlayer has moved to the top of the film after rapid thermal annealing, working as the diffusion barrier for upper Ni atoms. The three-dimensional surface morphology by atom force microscopy shows that the agglomeration of NiSi is effectively suppressed, which is attributed to the barrier effect of the Hf interlayer. The fabricated Ni(Hf)Si/Si Schottky diodes still displays good current-voltage characteristics even after annealed at temperatures varied from 650 °C to 800 °C, which further show that the Hf interlayer can improve the thermal stability of NiSi.     

Thermal stability of Ni silicide films on heavily doped n and p Si substrates

Electrical and structural properties of Ni silicide films formed at various temperatures ranged from 200 °C to 950 °C on both heavily doped n⁺ and p⁺ Si substrates were studied. It was found that surface morphology as well as the sheet resistance properties of the Ni silicide films formed on n⁺ and p⁺ Si substrates at the temperatures higher than 600 °C were very different. Agglomerations of Ni silicide films on n⁺ Si substrates begin to occur at around 600 °C while there is no agglomeration observed in Ni silicide films on p⁺ Si substrates up to a forming temperature of 700 °C. It was also found that the phase transition temperature from NiSi phase to NiSi₂ phase depend on substrate types; 900 °C for NiSi film on n⁺ Si substrate and 750 °C for NiSi film on p⁺ Si substrate, respectively. Our results show that the agglomeration is, especially, important factor in the process temperature dependency of the sheet resistance of Ni silicides formed on n⁺ Si substrates.     

Effect of lateral dimensional scaling on the thermal stability of poly-CoSi2 reacted on Si (001)

The effect of lateral dimensional scaling on the thermal stability of polycrystalline cobalt disilicide wires reacted on Si (001) has been studied down to 0.6 μm linewidth. An unpatterned silicide has been used as a reference sample. The annealing processes were performed in N₂ environment, between 900 and 1050°C, on both blanket and patterned silicide. Transmission electron microscopy analyses in plan-view and cross-section allowed us to study the morphology of lines before and after high-temperature processes. Resistance measurements showed a better thermal stability in blanket silicide layer compared to narrow lines. The electrical behaviour of the lines has been explained in terms of both lateral roughness and hole formation in the silicide layer.     

Silicide pre-clean effects on NiPtSi thermal stability for 65 nm technologies and beyond

The effects of different surface preparations on NiPtSi thermal stability were studied. HF wet clean, argon sputter etch and remote plasma pre-clean were used as silicide pre-cleans prior to NiPt sputter deposition and subsequent silicidation on blanket and patterned Si wafers. NiPtSi was characterized using SIMS, ellipsometry, voltage contrast (ES25) testing and electrical performance measurements of 65 nm test structures. Results show that when an in situ remote plasma pre-clean is used in addition to a classical HF wet clean to remove native oxide from the Si substrate prior to NiPt deposition and silicidation, Rs uniformity and SRAM electrical performance as a function of thermal budget are significantly improved. Rs measurements of patterned wafers and SIMS analysis of blanket wafers strongly suggest that the absence of native oxide prior to NiPt deposition and the presence of fluorine at the NiPtSi/Si interface play a key role in improving NiPtSi thermal stability.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

Nickel silicide formation on Si(100) and Poly-Si with a presilicide N2 + implantation

The key feature of this study is to incorporate N₂ ⁺ implant prior to Ni sputtering on the poly-Si gate and source/drain regions. The results show that the incorporation of the presilicide N₂ ⁺ implant is able to suppress agglomeration in the Ni silicide films up to 900°C and enhance the phase stability of NiSi on Si(100) up to 750°C. Stable and low sheet resistance was achieved on the silicided undoped poly-Si up to 700°C due to reduced layer inversion, which is driven by grain boundary energy and the surface energy of the poly-Si.     

Nitrogen impurity effects on nickel silicide formation at low temperatures - New “nitrogen co-plasma” approach

Nickel based silicide films were prepared by annealing nickel-platinum layers deposited on n doped Si substrates. We report on the evolution of the phase formation and the redistribution of contaminants on blanket wafers during silicide formation as a function of the nitrogen gas flow introduces during Ni(Pt) deposition. Nitrogen incorporation creates a contamination as-deposited layer which modifies phase formation and changes nickel diffusion. Nitrogen is not incorporated in silicide formed. After a second anneal, the monosilicide forms excepted for high nitrogen quantity introduced where the Ni₃Si₂ is always observed. Monosilicide thermal stability is also improved by nitrogen co-plasma.     

Investigation of iridium as a gate electrode for deep sub-micron CMOS technology

The physical and electrical properties of an Ir/SiO₂/Si stack were evaluated for advanced gate electrode application. The thermal stability of the stack was studied on MOS capacitors annealed at temperatures between 500 and 1000 °C in N₂ ambient for 30 s followed by forming gas anneal (FGA) at 420 °C for 20 min. The work function of iridium, found to be 4.9 eV, is stable up to 900 °C, making it a good candidate as PMOS electrode. In addition, no evidence was found for any chemical reaction at the interface between Ir and SiO₂.     

Roughness improvement of the CoSi2/Si-interface for an application as buried silicide

The material CoSi₂ is preferred for the fabrication of buried silicide films between silicon device layer and buried oxide of SOI substrates for BICMOS integrations. Such an application needs excellent quality of the interface between the silicide and the silicon device layer. Using the conventional cobalt salicide process the roughness and waviness of the interface is too large for a device application. In this presentation three technologies to improve the CoSi₂/Si-interface quality were characterized. Using the first technology a very thin single crystalline CoSi₂ film was fabricated on a silicon substrate. This film acts as initial layer to produce thicker single crystalline silicide films. By the second technology an interlayer between cobalt and the silicon substrate was used to mediate an epitaxial CoSi₂ growth. Different types and materials were tested. Using the third technique a sacrificial layer of polycrystalline silicon between cobalt and the silicon substrate was consumed during the silicidation reaction. This method gives the best results with interface roughness values of less than 1 nm. The interface roughness was measured after CoSi₂ removal using AFM. A possible epitaxial growth of the silicide films was investigated with XRD analysis. Cross sectional SEM images were prepared to analyze the interface waviness and the CoSi₂ structure.     

Microfabrication of a nickel mold insert by a modified deep X-ray lithography process and its application to hot embossing

In the present study, a modified deep X-ray lithography process is utilized for an efficient fabrication of precise metallic mold insert. A bare bulk polymethylmethacrylate (PMMA) sheet is used without any substrate as an X-ray photoresist in order to achieve a stable fabrication by avoiding a generation of a secondary radiation during a deep X-ray lithography process. The patterned PMMA sheet after development is then bonded on a metallic substrate using adhesive layers. The adhesive layers on the opened region of the patterned PMMA sheet are subsequently removed by X-ray exposure of short duration time. The next procedure is an electroplating process onto the opened area in the PMMA sheet, consequently resulting in the final mold insert. In this manner, a robust metallic mold insert for a mass replication of microstructures could be realized quite efficiently. The present fabrication method is confirmed by an example with a replication of microchannels via hot embossing process.     

Towards the implementation of advanced random access schemes for satellite IoT

Machine‐to‐machine (M2M) communications being pivotal for internet of things (IoT) networks are characterized by low‐cost, low complexity, and often energy constrained terminals with low traffic duty cycle. Satellite networks provide an attractive low‐cost solution for such application, in particular when the terminals (both fixed and mobile) are distributed over a wide geographical area not well served by terrestrial infrastructure. An ALOHA random access (RA) scheme is a natural candidate for M2M communications since it is well matched to sporadic traffic, and it requires little terminals coordination. However, the classical ALOHA scheme suffers from a low throughput when operated in a load region requiring low probability of packet loss. To overcome this intrinsic ALOHA limitation, in the last decade, a lot of effort has been devoted to the investigation of evolutions of the ALOHA scheme reducing the probability of destructive packet collisions thus making it more attractive for satellite IoT. In such context, the Contention Resolution Diversity ALOHA (CRDSA) scheme and the Asynchronous Contention Resolution Diversity ALOHA (ACRDA) have emerged as promising solutions thanks to their high spectral efficiency achievable with low packet loss probability. The results reported in literature are however assuming ideal demodulator performance. This paper investigates the design and optimization of RA burst demodulator algorithms for single‐frequency and multifrequency CRDSA and ACRDA. It evaluates the performance of such algorithms in a number of system scenarios of practical interest and studies the impact of relevant system parameters on several performance metrics.     

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Ω input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle.     

0.13微米硅化物 CMOS工艺下版图参数对栅极接地 NMOS晶体管骤回特性的影响

本文中,在 0.13微米硅化物 CMOS工艺下, 设计了不同版图尺寸和不同版图布局的栅极接地 NMOS器件。TLP测量技术用来获得器件的骤回特性。 文章分析了器件版图参数和器件骤回特性之间的关系。TCAD器件仿真软件被用来解释证明这些结论.通过这些结论,电路设计者可以预估栅极接地NMOS器件在ESD大电流情况下的特性,由此在有限的版图面积下设计符合 ESD保护要求的栅极接地 NMOS器件。本文同时给出了优化后的 0.13微米硅化物工艺下 ESD版图规则。     

一种用于无线植入式神经控制信号传输的低功耗BPSK解调器的CMOS实现

本文提出了一种新的BPSK解调器。在这个解调器中,设计了一种结构非常简单的时钟倍频器电路来代替传统BPSK解调器中的模拟乘法器,使得所设计的解调器电路结构简单、功耗较低,从而更适合于无线植入式神经记录系统中体内部分的单芯片设计。所提出的BPSK解调器采用Global Foundries 0.35 ?m 3.3 V标准CMOS工艺实现,芯片面积仅0.07 mm2,功耗只有0.5 mW。芯片测试结果证明它能正常工作。     

增量式光电编码器信号处理电路的设计与实现

实践中经常会遇到将光电编码器的输出信号经一系列处理转化成电压信号的情况。因此,以2RHIB型光电编码器为例,设计了一种集编码器信号接收、光电隔离、鉴相、频率电压转化和电压调整输出功能于一体的综合性电路,并对电路各组成部分作了较为详细的分析和阐述。实践证明,该电路通用性强、操作简单、性能可靠、实用性强。     

DVB流合成卡的设计与实现

介绍了基于 ＰＣＩ总线,利用 ＰＣＩ总线控制器 Ｓ５９２０和 ＤＳＰ芯片 ＴＭＳ３２０Ｃ３１所设计的 ＤＶＢ流合成卡,并提供了Ｓ５９２０及该卡的软、硬件说明。