应变SiGe SOI量子阱沟道PMOSFET阈值电压模型研究

在绝缘层附着硅(SOI)结构的Si膜上生长SiGe合金制作具有SiGe量子阱沟道的SOI p型金属氧化物半导体场效应晶体管(PMOSFET)，该器件不仅具有SOI结构的优点，而且因量子阱中载流子迁移率高，所以进一步提高了器件的性能.在分析常规的Si SOI MOSFET基础上，建立了应变SiGe SOI 量子阱沟道PMOSFET的阈值电压模型和电流-电压(I-V)特性模型，利用Matlab对该结构器件的I-V特性、跨导及漏导特性进行了模拟分析，且与常规结构的器件作了对比.模拟结果表明，应变SiGe SOI量子阱沟道PMOSFET的性能均比常规结构的器件有大幅度提高. 关键词： 应变SiGe SOI MOSFET 阈值电压 模型     

SOI波导光传输损耗和端面耦合损耗的精确测量与理论分析（英文）

采用法布里-珀罗(Fabry-Perot)谐振腔(也称F-P腔)方法测试SOI波导光传输损耗及其与光纤的端面耦合损耗的测量精度,对具有相同尺寸长度为8.37 mm的三条SOI波导通道进行测量,得到SOI波导光传输损耗和端面耦合损耗的平均值与测量精度值,且测量精度偏差值很小。通过温度的自动控制扫描仪对另一条长度为12.5 mm的SOI波导进行三次重复测量,获得的传输损耗值和端面耦合损耗值相同,说明采用F-P腔方法获得的测量精度值很稳定。建立了SOI波导传输损耗测量精度da/a与F-P腔谐振输出功率极限值消光比的相对误差dtM/tM和SOI波导端面菲涅耳反射系数的相对误差d R/R之间关系的理论模型。模拟结果表明:改变SOI波导上、下包层和芯层折射率,对光传输损耗和波导-光纤端面耦合损耗的测试精度无影响。数值模拟结果与实验测试结果相一致。     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diffused metal\ben oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel low-density metal-oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.     

集成光学

集成光学、波导理论 TN252 2004021174 基于SOI的光子晶体波导的研究=Study of SOI-based photonic crystal waveguides[刊,中]／解灵运(清华大学电子工程系．北京(100084))．张冶金…∥半导体光电．一2003,24(6)．—392-395 给出了基于SOI晶片,带隙中心位于1550 nm的光子带隙材料及光子晶体波导器件的设计方法。采用基于超原胞的平面波展开法和基于完美匹配层边界条件的三维时域有限差分法,对二维光子晶体平板的带隙结构及光波传输进行仿真。在大量计算和优化的基础上,设计了适于248mm深紫外曝光和0．18μm离子束刻蚀工艺的光子晶体带隙材料及波导器件,得到了初步的工艺实验结果和样品SEM测试结果。图4参10(严寒)     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

SOI纳米线波导导光机理的物理分析

SOI（silicon-on-insulator）纳米线波导及其器件是近年来光电子学领域研究的重点内容之一．文章从基本的导波光学理论出发,引入古斯一汉森位移理论,对SOI纳米线波导导光的物理机制进行了分析并给出了物理解释和模拟结果．     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Investigation on a solution to improve the irradiation reliability of SOI NMOSFET

A solution is developed to improve the irradiation reliability of SOI NMOSFET (N-type Metal Oxide Semiconductor Field Effect Transistor). This solution, including SOI (Silicon On Insulator) wafer hardening and transistor structure hardening, protects the SOI circuit from total dose irradiation effect.     

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance(R on,sp) silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(pLDMOS) compatible with high voltage(HV) n-channel LDMOS(nLDMOS) is proposed.The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state(BP SOI pLDMOS).Its superior compatibility with the HV nLDMOS and low voltage(LV) complementary metal-oxide semiconductor(CMOS) circuitry which are formed on the N-SOI layer can be obtained.In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping,leading to an enhanced(reduced) surface field(RESURF) effect.The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage(BV) but also a significantly reduced Ron,sp.The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μm,and R on,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2.Compared with the PW SOI pLDMOS,the BP SOI pLDMOS also reduces the R on,sp by 34% with almost the same BV.     

电磁波辐照下量子线的电子自旋极化输运性质

理论上研究Rashba自旋-轨道相互作(SOI)量子线在外电磁波辐照下的电子自旋极化输运性质.在自由电子模型下利用散射矩阵方法,发现当Rashba SOI较弱时,自旋极化率与外电磁场频率和电子入射能量无关,而当Rashba SOI较强时,自旋极化率则强烈依赖于外场频率和电子入射能量,其物理根源是Rashba SOI使子带混合引起的.此外,当电子的入射能量增加到打开另一通道阈值时,电子的透射率出现一个反常的台阶结构,这来源于电子与光子的非弹性散射而使电子在子带间的跃迁. 关键词： 量子线 电磁波 自旋极化输运 散射矩阵     

A New silicon—on—Insulator Structure of Metal—Oxide—Semiconductor Field Effect Transistor to Reduce Self—Heating Effect

A new silicon-on-insulator(SOI)device stucture is proposed.This new design provides a new path to reduce the temperature of the channel of SOI metal-oxide-semiconductor field effect transistor(MOSFET).The device has been verified in two-dimensional device simulation,The new structure reduces the self-heating effect of SOI MOSFET and decreases the negative differential transconductance.     

基于SOI技术的单层多晶EEPROM和SONOS EEPROM抗总剂量辐照特性研究

在自行研发的0.8 μm SOI工艺平台上开发了基于SOI技术的单层多晶硅EEPROM(electrically erasable programmable read only memory)和SONOS (silicon-oxide-nitride-oxide-silicon)EEPROM,并进行了抗总剂量辐照实验研究,分析了各种EEPROM结构在抗总剂量辐照下的失效机理.结果表明基于SOI 技术的SONOS EEPROM具有良好的抗总剂量辐照性能,为抗辐照EEPROM电路中的存储单元结构选取提供了依据. 关键词： EEPROM SOI SONOS 辐照 浮栅     

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium(SiGe) heterojunction bipolar transistor(HBT) on thin silicon-on-insulator(SOI) has recently been demonstrated and integrated into the latest SOI BiCMOS technology.The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion,which is different from that of a bulk counterpart.A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation.The Early voltage shows a kink with the increase of the reverse base-collector bias.Large differences are observed between SOI devices and their bulk counterparts.The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design,the simulation and the fabrication of high performance SOI SiGe devices and circuits.     

集成光学 光电集成与器件

TN2562006010418超紧凑型SOI基3×3MMI波导光开关的优化设计=Op-ti mal design of ultra-compact3×3SOI MMI optical swit-ches[刊,中]/贾晓玲(同济大学电子科学与技术系.上海(200092)),高凡…∥半导体光电.—2005,26(4).—294-298提出一种基于SOI材料的超紧凑型3×3MMI波导光开关,开关仅有一个多模波导,且多模波导采用更为紧凑的双曲结构。用FD-BPM方法对其各个状态进行了模拟和分析,并对器件的结构参数进行了优化设计。结果表明,这种光开关可以成功实现任意两输入和输出通道间的开关功能,优化后的开关呈现优良的综合性能,且整…     

A comparative study of YBa2Cu3O7-δ/YSZ bilayer films deposited on silicon-on-insulator substrates with and without HF pretreatment

Highly epitaxial YBa2Cu3O7-δ (YBCO) and yttria-stabilized zirconia (YSZ) bilayer thin films have been deposited on silicon-on-insulator (SOI) substrates by using in situ pulsed laser deposition (PLD) technique. In the experiment, the native amorphous SiO2 layers on some of the SOI substrates are removed by dipping them in a 10% HF solution for 15 s. Comparing several qualities of films grown on substrates with or without HF pretreatment, such as thin film crystallinity, general surface roughness, temperature dependence of resistance, surface morphology, as well as average crack spacing and crack width, naturally leads to the conclusion that preserving the native SiO2 layer on the surface of the SOI substrate can not only simplify the experimental process but can also achieve fairly high quality YSZ and YBCO thin films.     

封面说明——干净的重要性

绝缘基硅晶片（silicon-on—insulator简称SOI）是一种将导电硅膜覆于绝缘氧化硅基底的技术．这种技术目前发展迅猛，广泛地用于高速电子电路和传感器．SOI大部分期望性能依赖于将硅膜做得尽可能薄，但是随着研究者们将硅膜做得越薄，他们就越担心由硅晶体缺陷在接触面产生的载流子会破坏材料的电学性质．     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n~+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n +-layer silicon-on-insulator (PBN SOI) is proposed in this paper.Based on the proposed expressions of the vertical interface electric field,the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I),resulting in a high breakdown voltage (BV) for the device.For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 μm),the E I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI,respectively.     

SOI新结构——SOI研究的新方向

SOI(silicon-on-insulator绝缘体上单晶硅薄膜)技术已取得了突破性的进展,但一般SOI结构是以SiO2作为绝缘埋层,以硅作为顶层的半导体材料,这样导致了一些不利的影响,限制了其应用范围.为解决这些问题和满足一些特殊器件/电路的要求,探索研究新的SOI结构成为SOI研究领域新的热点.如SOIM,GPSOI,GeSiOI,Si on AlN, SiCOI, GeSiOI,SSOI等.文章将结合作者的部分工作,报道SOI新结构研究的新动向及其应用.     

Magnetic quantum oscillations in a monolayer graphene under a perpendicular magnetic field

The de Haas-van Alphen(dHvA) oscillations of electronic magnetization in a monolayer graphene with structureinduced spin-orbit interaction(SOI) are studied.The results show that the dHvA oscillating centre in this system deviates from the well known(zero) value in a conventional two-dimensional electron gas.The inclusion of SOI will change the well-defined sawtooth pattern of magnetic quantum oscillations and result in a beating pattern.In addition,the SOI effects on Hall conductance and magnetic susceptibility are also discussed.     

SOI SiGe HBT结构设计及频率特性研究

将SOI技术优势引入SiGe HBT,可满足当前BiCMOS高速低功耗的应用需求.SOI SiGe HBT作为BiCMOS工艺的核心器件,其频率特性决定了电路所能达到的工作速度.为此,本文针对所提出的SOI SiGe HBT器件结构,重点研究了该器件的频率特性,并通过所建立的集电区电容模型予以分析.规律和结果为:1)SOI SiGe HBT特征频率随集电区掺杂浓度的升高而增加;2)SOI SiGe HBT特征频率与集电极电流IC之间的变化规律与传统SiGe HBT的相一致;3)正常工作状态,SOI SiGe HBT(集电区3×1017cm-3掺杂)最高振荡频率fmax大于140 GHz,且特征频率fT大于60 GHz.与传统SiGe HBT相比,特征频率最大值提高了18.84%.以上规律及结论可为SOI SiGe HBT及BiCMOS的研究设计提供重要依据.