Integrated IGBT short-circuit protection structure: Design and optimization

Generally, short-circuit protections for IGBT are provided by the assistance of analogical discrete devices which can sense and protect. In this paper, we present a new NPT IGBT structure with integrated short-circuit protection. This structure is composed of an anode voltage sensor, a delay MOS transistor, a MOS transistor allowing IGBT turn-off and a Zener diode. The structure optimization depends on the flexible technological process developed for power structures and based on the functional integration concept [1]. The protection structure optimization is presented and its functionality is verified by 2D simulations with ISE TCAD.     

一种双发射极沟槽栅超结IGBT

本文对传统沟槽栅超结IGBT进行了改进,得到一种沟槽栅双发射极超结IGBT,本结构第一个发射极区域和传统IGBT结构一样能够发射电子、接收空穴,在p型柱顶部的第二个发射极区域能够起到空穴分流的作用,在有效地提高器件抑制闩锁的能力的同时,保持了超结IGBT器件的高击穿电压(BVoff)和低关断损耗(Eoss)。仿真显示在VGE=10V的条件下,改进结构的闩锁电流从15000A/cm2 提升至 28300A/cm2,器件的击穿电压为810V,在导通压降为1.2V的条件下,关断损耗为6.5 mJ/cm2。     

Small organic additive to improve the charge separation in an inverted bulk heterojunction organic photovoltaic

A small organic molecule of 2,3-bis(5-bromothiophene-2-yl)acrylonitrile (DTDBAL) was synthesized for the first time and introduced into an active layer consisting of poly-3-hexylthiophene (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM), in order to improve the performance of an inverted bulk heterojunction organic photovoltaic. The short-circuit current of the device was improved owing to the formation of a cascade band alignment of P3HT/DTDBAL/PCBM which enhanced the exciton dissociation and charge transport. Meanwhile, the open-circuit voltage and fill factor were simultaneously improved due to the optimization of the active layer morphology. The best power conversion efficiency achieved was 3.45% under simulated AM 1.5G illumination of 100 mW/cm², which is an increase of 36% compared to a solar cell without the additive and featuring only P3HT/PCBM as the active layer.     

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.     

带有固定延迟时间的IGBT去饱和过流检测电路

提出了一款带有固定延迟时间的绝缘栅双极型晶体管(IGBT)去饱和(DESAT)过流检测电路。在IGBT去饱和过流检测电路中加入固定延时电路,当检测到过流信号后关断IGBT,防止IGBT被烧毁。同时固定延时电路开始计时,经历了固定延迟时间后,电路错误信号清除,IGBT恢复正常工作状态,提高了IGBT功率回路的可靠性与安全性。将固定延时电路集成在IGBT驱动芯片中,提高了系统的集成度。采用UMC 0.6μm高压BCD工艺模型对去饱和过流检测电路进行前仿和后仿。仿真结果表明,采用线性温度补偿方法,基准电路的过流阈值电压典型值为6.97 V,温度系数为19.5×10^-6/℃。IGBT开启后消隐时间为920 ns。在不同工艺角仿真中,后仿固定延迟时间在2.8~4 ms之间变化,典型值为3.3 ms,使功率回路储能元件中的冗余能量充分释放。     

高压工艺下针对射频LDMOS器件栅氧的静电保护设计

由于高压工艺的独特性以及静电保护在不同工艺下不可移植的特点,针对射频LDMOS需要进行全芯片静电保护设计与研究以防止器件受到静电损伤。本文针对射频LDMOS栅氧进行了静电保护设计并探究了高压工艺下器件参数对静电保护鲁棒性的影响。通过对实验和二维器件仿真结果的分析讨论,为射频LDMOS栅氧设计了具有高维持电压和静电保护窗口灵活可调特性的级联NMOS作为集成静电保护器件。     

军用电子设备抗高功率微波技术分析

基于对高功率微波(HPM)的效应、环境、耦合通道,对军用电子设备的HPM加固战略和加固关键技术作了论述,并针对某雷达的HPM防护进行了研究,提出了解决一般电子设备抗HPM的思路和研究方向,为今后深入研究打下基础。     

带有业务感知分类的低开销保护策略

为将IP业务准确分类,并根据所分优先级类别进 行高效合理的区分保护,提出一种带有业务感知分 类的网络保护策略(PSTAC)。定义信息重要度(IS)感知业务特征 ,结合贝叶斯理论建立业务优先级分类模型,并考虑不 同级别业务的QoS参数进行针对性保护。仿真结果表明,所提PSTAC实现了高精度的业务分类 ,且比传统的区分保护策略有更高的资源利用率和更低的网络阻塞率。     

Design of fabrication of ESD protection circuit with high holding voltage for power IC

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.     

探究电子信息工程技术的发展及保障途径

随着快速发展的社会经济,我国科学技术水平显著提升,在人们的日常生活中对电子产品的依赖程度不断加深,在各个行业和领域中都广泛的应用了各种电子信息技术.为了实现电子信息工程技术的顺利发展,就必须加强保障,这样才能够实现其顺利发展.本文主要是从电子信息工程技术的发展方向以及保障电子信息工程技术发展的有效途径这两个方面对电子信息工程技术做出了详细的分析和研究,这样不仅仅能够帮助确定电子信息工程技术正确的发展方向,加快提高电子信息工程技术水平和质量,同时也能够为电子信息工程技术的发展营造出安全、良好的发展环境,保证其得到有效发展,更好的发挥出电子信息工程技术的有效作用.     

GH-039带有过电流保护功能的高速大容量IGBT厚膜驱动器集成电路

介绍了带有过电流保护功能的高速大容量IGBT厚膜驱动器GH－039,分析了它的引脚排列和各引脚的名称,功能和用法,给出了它们的主要设计特点和参数限制,剖析了其的内部结构和工作原理,进而探讨了其应用技术。它单电源工作,内置高速光电耦合器实现输入、输出隔离;它高密度集成,具有对被驱动IGBT进行过电流或短路保护的功能,可用来直接驱动300A、600V的功率IGBT模块。     

Shared partial path protection in WDM networks with shared risk link groups

For 100% shared risk link group (SRLG) failure protection, conventional full path protection has to satisfy SRLG-disjoint constraints, i.e., its working path and backup path cannot go though the same SRLG. With the increase of size and number of SRLGs, capacity efficiency of conventional shared full path protection becomes poorer due to SRLG-disjoint constraints and the blocking probability becomes much higher due to severe traps. To solve these problems, we present a partial path protection scheme where SRLG-disjoint backup paths may only cover part of the working path. Full path protection becomes a special case of partial path protection, in which the backup path covers the full working path. By choosing the most survivable partial backup path as backup path, we can make the impact of SRLG failures as low as possible and accept as many as possible connection requests. Assuming every SRLG has the same probability to fail, we present a heuristic algorithm to find the most survivable partial backup path by choosing full path protection first, iteratively computing partial backup paths and choosing the most survivable one. The benefit of this heuristic algorithm is that it can find the optimal results within less iteration. Analytical and simulation results show that, compared to conventional full path protection, our proposed scheme can significantly reduce blocking probability with little sacrifice on survivability. The proposed scheme is very useful particularly when the network contains a lot of SRLGs and the blocking probability of conventional full path protection becomes too high.

双极双栅MOS晶体管静态特性解析模型的模拟与分析

提出了一种应用于VHF和UHF的新型功率电子器件－双极双栅MOS晶体管（BDGMOSFET）,该结构是在单栅MOSFET一侧引入双极型压控晶体管（BJMOSFET）,使之在正向工作时具有MOSFET和BJT的工作特性,通态电较小,同时,减少了寄生双极晶体管效应,改善了频率特性。文章对其静态特性的解析模型进行了详细研究,在该模型基础上运用通用电路模拟软件PSPICE的多瞬态分析法模拟了BDEMOSFET的直流特性,结果表明,在同等条件下,BDGMOSFET的电流密度比双栅MOSFET提高大约30％。     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

负载感知的低开销网络保护机制研究

为提高资源利用率和降低网络阻塞率,提出一种应用于光网络中带有负载感知(LA)的低开销保护机制,充分考虑了网络共享风险链路组(SRLG)的约束条件,建立整数线性规划(ILD)模型对共享通道保护策略与LA技术进行联合优化。仿真表明,与传统机制相比,所提出的机制能够有效地降低网络阻塞以及保护开销,使网络中的流量更加均衡。     

一种Xilinx FPGA有效配置位保护方法

机载电子设备中广泛采用的静态随机存储器(Static Random Access Memory,SRAM)型现场可编程门阵列(Field Programmable Gate Array,FPGA)易受到大气中子辐射的影响而发生单粒子翻转.为了提高抗干扰能力,针对SRAM型FP GA需要进行抗单粒子翻转防护,提出了一种X...     

OFDM-PON系统中基于混沌映射的密钥保护和PAPR降低的加密算法

针对正交频分复用-无源光网络(OFDM-PON) 传输系统中的数据安全与高峰均功率比(PAPR)问 题,提出一种基于混沌映射的PAPR降低与数据加密算法。该加密算法,首先利用拉格朗日多 项式隐藏混 沌映射初值实现密钥保护;然后,利用混沌映射生成二值序列,通过正向异或与反向异或对 明文进行加密 得到动态密文,以抵抗选择明文攻击;最后,采用混沌加密的恒包络零自相关(CAZAC)矩 阵与OFDM符 号相乘降低PAPR。实验结果表明,该加密算法可实现密钥的隐藏,且生成的动态密文能够有 效抵抗选择明 文攻击。同时,相较于普通的OFDM-PON系统,该算法能够实现~2.4 dB(PAPR=10－3 )的PAPR降低与~1dB(BER=10－3)的接收灵敏度提升,进一步提升了传输性能。     

Organic field-effect transistor with extended indium tin oxide gate structure for selective pH sensing

In this study, organic field-effect transistors (OFETs) with extended gate structure were fabricated for selective pH sensing applications. Indium tin oxide (ITO) was used as extended gate electrode as well as an active layer for H⁺ sensing. The threshold voltage of the fabricated ion-selective OFET was varied by the changes in the electrochemical potential at the ITO electrode surface upon its exposure to buffer solutions with variable pH values. The sensor showed excellent linearity and a high sensitivity of 57–59 mV/pH in the pH range of 2–12. The selectivity of the ITO sensing layer to H⁺ ions was also investigated by measuring the interfering effect of Ca²⁺ and K⁺ ions in the buffer pH solutions. The results showed that the Ca²⁺ and K⁺ ions weakly interfere with the selective pH sensing of the ITO-extended gate OFET sensor device.     

电子系统的避雷设计

为了预防和避免雷电对电子系统设备造成破坏,研究了电子系统的避雷设计,包括直击雷防护、感应雷防护、架高天线防护、地网设置等方面,并用实例进行了验证.