Study of the UBM to copper interface robustness of solder bumps in flip chip packages

Shear tests on SnAg solder bumps were performed with a reduced height to the surface for a high shear force on the under bump metallurgy (UBM) to redistribution layer (RDL) copper interface. By this the failure mechanism of UBM–RDL delamination after stress tests simulating several assembly reflows could be reproduced. A design of experiment was done with corner wafers at worst case conditions for topography and interface clean. TEM cross sections confirmed nano scale carbon residues in the interface when reducing the clean efficiency. This results in a mechanically weakened interface with a present electrical contact. The shear test with reduced height is a more severe test beyond the JEDEC test to verify the bump robustness. This is important when existing bump technologies are used for flip chip package solutions with increased solder reflow requirements.     

Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages

As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked Back End of Line (BEoL) structures has been developed for reducing R-C delay in order to obtain high-speed signal communication. However, its reliability might become a concern owing to the considerably lower adhesive strength, as well as the greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper, the global-local finite element method, specified boundary condition (SBC) method, is employed as a bridge to estimate the impact from package level to the deep submicron BEoL structure of the flip chip package. The results show that the defect in the stacking structure at the center of the silicon has a lower tendency to crack than that at the corner region. In addition, the higher underfill CTE shows the disadvantage of the defect.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.     

Failure mechanism of lead-free solder joints in flip chip packages

The failure mechanisms of SnAgCu solder on Al/Ni(V)/Cu thin-film, underbump metallurgy (UBM) were investigated after multiple reflows and high-temperature storage using a ball shear test, fracture-surface analysis, and cross-sectional microstructure examination. The results were also compared with those of eutectic SnPb solder. The Al/Ni (V)/Cu thin-film UBM was found to be robust enough to resist multiple reflows and thermal aging at conditions used for normal production purposes in both SnAgCu and eutectic SnPb systems. It was found that, in the SnAgCu system, the failure mode changed with the number of reflows, relating to the consumption of the thin-film UBM because of the severe interfacial reaction between the solder and the UBM layer. After high-temperature storage, the solder joints failed inside the solder ball in a ductile manner in both SnAgCu and SnPb systems. Very fine Ag₃Sn particles were formed during multiple reflows in the SnAgCu system. They were found to be able to strengthen the bulk solder. The dispersion-strengthening effect of Ag₃Sn was lost after a short period of thermal aging, caused by the rapid coarsening of these fine particles.     

High density of electrodeposited Sn/Ag bumps for flip chip connection

As peripheral pads in commercial chips have a pitch in the neighbourhood of 40-50 μm, a technique that could deposit solder paste directly in such pitch would be of great interest to reduce the overall cost of flip chip.This paper describes a new technique that can considerably reduce the final pitch. The main new feature of this process is that the bump pads can be built directly onto the peripheral ones. An electroplating process allows solder bump formation with a final pitch goal of 40-50 μm and after an accurate reflow process, eutectic Sn-3.5 wt%Ag solder bumps are obtained. In fact, the typical re-routing process can be eliminated and the process cost considerably reduced.     

Anisotropic behavior of the capillary action in flip chip underfill

An underfill encapsulant can be used to improve the long-term reliability of flip chip interconnecting system by filling the gap between the chip and substrate around the solder bumps. The underfill encapsulant was filled by a capillary flow. This study was devoted to investigate the anisotropic effects of the capillary action induced by the solder bumps. A modified Hele-Shaw flow model, considering the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. A capillary force model, depending on the direction of filling flow, for full array solder bumps was proposed. The capillary force was formulated based on quadrilateral arrangement of solder bumps. It was found that the capillary action is not the same for different directions. In the 45° direction, enhancement of the capillary flow was noticed for a bump pitch within a critical value. The edge preferential flow during the underfill experiment could be attributed to the anisotropic behavior of the capillary action.     

The effects of rheological and wetting properties on underfill filler settling and flow voids in flip chip packages

As the bump diameter and bump pitch of flip chip packages get smaller, the underfill becomes more resistant to flow. Therefore, low viscosity underfills are used in the process to increase the throughput. Problems associated with low viscosity underfills include filler settling and flow induced voids due to fast edge flow. In this paper, we will discuss how the rheological properties can affect underfill filler settling and flow voids. The effects of yield stress of underfill on filler settling and the effects of shear thickening of underfill at large shear rates on flow voids of underfill were investigated. It was shown that the underfills with small fillers have shear-thickening viscosity and yield stress. The filler settling of underfills with yield stress was greatly reduced. A video underfill flow metrology with quartz die packages was developed for flow void observation. The correlation between underfill, substrate properties, and flow voids formation based on the video underfill flow measurement will be discussed.     

Thermal resistance analysis and validation of flip chip PBGA packages

This work proposes a finite element numerical methodology to predict the thermal resistance of both flip chip-plastic ball grid array (FC-PBGA) with a bare die and FC-PBGA with a metal cap. The 3D finite element model was initially constructed to simulate the thermal resistance of FC-PBGA. A thermal resistance experiment was performed to verify the FEM results, following the construction of specimens of FC-PBGA with a bare die and with an aluminum cap, using six-layered substrate. The verified finite element model was employed to determine the thermal resistance of FC-PBGA with a copper cap using four-layered and six-layered substrates. Experimental results demonstrated that FC-PBGA with a metal cap improves thermal performance by 35% over with a bare die. FC-PBGA with a copper cap slightly improves thermal performance from 2% to 2.8% over that of FC-PBGA with an aluminum cap. The thermal resistance of FC-PBGA with a four-layered substrate is reduced by 4.0% to 5.9% from that of FC-PBGA with a six-layered substrate, since the four-layered substrate contains less metal. The finite element numerical results negligibly differ from the experimental results by 6% to 8.1%. A finite element numerical methodology is here proposed to predict the thermal resistance of FC-PBGA. The methodology is effective in researching and developing new products or improving existing packages.     

印制板焊接试验方法与测试评价

焊接试验方法是考察印制板质量和可靠性的重要方法之一,本文通过对3种具体试验方法的标准介绍和比较,结合实际试验案例进行原因分析,为PCB检验人员正确掌握以上试验方法提供技术指导。     

高密度LED焊点微空洞的X射线检测和分析

利用高精度X射线检测设备分别对用Sn37Pb焊膏和Sn3.0Ag0.5Cu焊膏组装的高密度LED灯板进行焊后和老化后的微空洞检测,观察了焊点的微空洞缺陷,并计算微空洞尺寸。结果表明:老化前微空洞面积与焊点面积比在10%~25%的,Sn3.0Ag0.5Cu焊点中约含25.5%,略大于Sn37Pb焊点的23.5%,且明显小于Sn3.0Ag0.5Cu焊点老化后的31.4%。两种焊点老化前后微空洞所占面积比都在<25%的合格范围内,但Sn3.0Ag0.5Cu焊点更易形成微空洞。     

Transmission property of flip chip package with adhesive interconnection for RF applications

The radio frequency (RF) and high frequency performance of the flip chip interconnects with anisotropic conductive film (ACF) and non-conductive film (NCF) was investigated and compared by measuring the scattering parameters (S-parameters) of the flip chip modules. Low cost electroless-Ni immersion-Au (ENIG) plating was employed to form the bumps for the adhesive bonding. To compare the accurate intrinsic RF performance of the ACF and NCF interconnect without lossy effect of chip and substrate, a de-embedding modeling algorithm was employed. The effects of two chip materials (Si and GaAs), the height of ENIG bumps, and the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip module were also investigated. The transmission properties of the GaAs were markedly improved on those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the RF performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the capacitive component between the bump and substrate and self inductance of the conductive particle surface in the ACF interconnect.     

Flux-free direct chip attachment of solder-bump flip chip by Ar + H2 plasma treatment

The flux-free flip-chip bonding process using plasma treatment was investigated. The effect of plasma-process parameters on Sn oxide-etching characteristics was evaluated by Auger depth-profile analysis. The die-shear test was performed to evaluate the adhesion strength of an Sn-37mass%Pb and Sn-3.5mass%Ag solder-bump flip chip that was bonded after plasma treatment. The Ar + H₂ plasma treatment reduced the thickness of the oxide layer on the Sn surface. The addition of H₂ to the Ar plasma improved the oxide-etching characteristics. A low chamber pressure was more effective in oxide etching. The die-shear strength of the plasma-treated Sn-Pb and Sn-Ag solder flip chip was higher than that of the nontreated chip but lower than that of the fluxed chip. The difference in the die-shear strength between the plasma-treated specimen and the nontreated specimen increased with increasing bonding temperature. The plasma-treated flip chip fractured at the solder/top-surface metallurgy (TSM) interface at low bonding temperature, but at the solder/under-bump metallurgy (UBM) interface at high bonding temperature.     

The law of ultrasonic energy conversion in thermosonic flip chip bonding interfaces

In this paper, the vibration characteristics during the flip chip (FC) bonding process were observed by using a laser Doppler vibrometer (LDV), and the atom diffusion features in vertical section of the FC bonding interfaces were inspected by using a high resolution transmission electron microscope (HRTEM). Results show that the vibration velocity of a die was about 500 mm/s during the traditional FC bonding process, and that of a substrate was only about 180 mm/s. It led to the difference of atom diffusion in the FC interfaces. For the given variables, the thickness of atom diffusion at an up-interface (i.e. Au/Al interface) of the FC bonding was about 500 nm where was an inter-metallic compound (i.e. AuAl₂), and that of atom diffusion at a down-interface (i.e. Au/Ag interface) was about 200 nm. Furthermore, the law of ultrasonic energy conversion was found that the ratio of the up-interface to the down-interface in the FC bonding was statistically about 2.21:1. According to this principle, different bonding processes are suggested to improve the performance of two interfaces. The experimental evaluation confirms the effectiveness of the suggested processes on minimizing the inter-metallic compound layer and equilibrating the thickness of atom diffusion at two interfaces.     

Dynamic strength of anisotropic conductive joints in flip chip on glass and flip chip on flex packages

The work presented in this paper focuses on the behavior of anisotropically conductive film (ACF) joint under the dynamic loading of flip chip on glass (COG) and flip chip on flexible (COF) substrate packages. Impact tests were performed to investigate the key factors that affect the adhesion strength. Scanning electron microscopy (SEM) was used to evaluate the fractography characteristics of the fracture. Impact strength increased with the bonding temperature, but after a certain temperature, it decreased. Good absorption and higher degree of curing at higher bonding temperature accounts for the increase of the adhesion strength, while too high temperature causes overcuring of ACF and degradation at ACF/substrate interface––thus decreases the adhesion strength. Higher extent of air bubbles was found at the ACF/substrate interface of the sample bonded at the higher temperature. These air bubbles reduce the actual contact area and hence reduce the impact strength. Although bonding pressure was not found to influence the impact strength significantly, it is still important for a reliable electrical interconnect. The behaviors of the conductive particles during impact loading were also studied. From the fracture mode study, it was found that impact load caused fracture to propagate in the ACF/substrate interface (for COG packages), and in the ACF matrix (for COF packages). Because of weak interaction of the ACF with the glass, COG showed poor impact adhesion.     

Effect of multiple reflows on interfacial reaction and shear strength of Sn-Ag electroplated solder bumps for flip chip package

The effect of displacement rate and intermetallic compound (IMC) growth on the shear strength of electroplated Sn-2.5Ag (in wt.%) flip chip solder with Cu under-bump metallization (UBM) were investigated after multiple reflows. Cu₆Sn₅ IMC was formed at the interface after one reflow. After five reflows, two different IMC layers, consisting of a scallop-shaped Cu₆Sn₅ phase and a planar Cu₃Sn phase, and their thicknesses increased with increasing reflow number up to 10. The shear strengths peaked after four reflows, and then decreased with increasing reflow number. Increasing displacement rate increased the shear force. The tendency toward brittle fracture characteristics was intensified with increasing displacement rate and reflow number.     

结型LED的热特性分析与工程设计

文章从半导体结型发光器件热特性的概念出发，导出了ＬＥＤ各种瞬态工作状态下输出功率与热特性的概念出发，导出了ＬＥＤ各种瞬态工作状态下输出功率与热特性参数的关系。分析讨论了ＬＥＤ输出光功率对不同电流脉冲的响应特性以及ＬＥＤ热特性的设计方法。     

Thermal investigation of LED array with multiple packages based on the superposition method

In this paper, the superposition method is used to investigate the complete temperature field of a light-emitting diode (LED) packaging substrate, based on the results of transient temperature rise measurements and the thermal resistance coupling matrix. The feasibility of use of the superposition method in an LED array with multiple packages has been proved first by temperature comparisons with the simultaneous operation of an array (5×5) of 25 high power LEDs mounted on a metal core printed circuit board (MCPCB). Compared with existing approaches, the superposition method will measure the internal temperature of chip directly, accurately and nondestructively. According to the relatively accurate and reliable self-heating and coupling temperature rise data, optimization scheme of LED lamp with multiple packages is proposed. The results show that increasing the heat source separation distance and improving the thermal conductivity of thermal interface materials will reduce the temperature rise and thermal non-uniformity.     

倒装芯片封装技术及内部应力检测技术探析

当前,倒装芯片封装技术已经成为相关领域的主流方法,但由于芯片、基板、焊球、下填料等材料具有差异化的热膨胀系数,导致封装过程中极易引入热应力,不利于保持芯片的性能及其可靠性。采用有效方法能够对倒装封装过程中所产生的应力进行检测,对于完善封装参数,提高产品可靠性,具有重要的现实意义。     

Thermal performance impacts of heat spreading lids on flip chip packages: With and without heat sinks

Heat spreading lids on a flip chip package can provide many thermal and mechanical advantages. Major drawbacks are higher module costs and potentially poorer thermal performance with a heat sink. This study compares thermal performance of direct lid attach (DLA) and bare die flip chip packages and addresses the roles of interface resistance and lid thickness. The IBM SLC^TM package is tested and modeled. JEDEC standard wind tunnel tests as well as CFD models are used for analysis. The study reveals that the DLA design without additional heat sinking can provide significantly better thermal performance compared to the bare die package, depending on package size and airflow rate. With a heat sink the performance of the lidded package can be superior or inferior depending on interface resistance, lid design and the standard used for comparison.