Multidimensional digital filtering by using parallel algorithms based on diagonal processing

An approach for massive parallel processing in multidimensional digital filtering, which has briefly been introduced for causal digital filters in previous publications, is generalized and examined in more detail. It is based on a suitably modified sampling procedure combined with diagonal processing and does not require any additional arithmetic operations in comparison with corresponding conventional digital filtering. The condition that has to be satisfied for making the approach suitable for full parallel processing is derived. Properties of diagonal hyperplanes as required for the present approach are discussed.     

Extending the concept of IIR filtering to array processing using approximate spatial IIR structure

Various array processing techniques applied to uniform linear arrays are involuntarily realized using structures that are analogous to finite impulse response filters. This observation leads to the following question: “can we extend infinite impulse response (IIR) filtering to array processing?”. In this paper, we introduce the concept of IIR array in spatial domain. Note that IIR array here does not mean time-domain IIR filtering for array beamforming which is commonly understood. This paper is dedicated to the study of an alternate approach for array signal processing which defines IIR structure in spatial domain. To illustrate the applicability of the concept of IIR array, we propose a new direction-of-arrival estimation technique as well as a beamformer with the spatial domain IIR array implementation. The performance of the proposed methods are comparable to the existing techniques. These illustrations are intended to introduce a new approach which potentially can offer more degrees of freedom to control the performance of the array and reduce the complexity of the system for a desired performance.     

Low-power filtering via adaptive error-cancellation

A low-power technique for digital filtering referred to as adaptive error-cancellation (AEC) is presented in this paper. The AEC technique falls under the general class of algorithmic noise-tolerance (ANT) techniques proposed earlier for combating transient/soft errors. The proposed AEC technique exploits the correlation between the input and soft errors to estimate and cancel out the latter. In this paper, we apply AEC along with voltage overscaling (VOS), where the voltage is scaled beyond the minimum (referred to as V/sub dd-crit/) necessary for correct operation. We employ the AEC technique in the context of a frequency-division multiplexed (FDM) communication system and demonstrate that up to 71% energy reduction can be achieved over present-day voltage-scaled systems.     

Low-power CMOS digital design

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption     

Low-power MIMO signal processing

In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.     

Reduced-complexity digital filtering structures using primitive operations

The letter presents a class of algorithms which generate filtering structures with reduced numbers of elementary operations. The directed acyclic graphs which result completely describe the device structure, and may be mapped directly into hardware or software realisations.     

Approximate processing for low-power digital filtering usingvariable canonic signed digit coefficients

An alternative approximate processing method which dynamically adjusts the precision of the canonic signed digit (CSD) coefficients is proposed. This proposed method employs a two-stage search for finding approximated values of CSD coefficients. Experimental results show that the number of additions is reduced to 29.4%, 11.8%, and 3.9% for each approximation level     

Low-power digital neuron for SOM implementations

A digital implementation of the self-organising map (SOM) is shown to have reduced power requirements through a strategy of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs requiring two clock cycles, one clock cycle, and half clock cycle per element of the input vector have been constructed and analysed. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%.     

Low-power digital communication with unterminated transmissionlines

Conventional telecommunication techniques are optimized to communicate over long distances (>1 mi), subject to high attenuation, high crosstalk, and other deteriorations in transmission. A trend in telecommunication system architectures is to disperse the previously centralized switching centers, thereby providing switching within a few hundred feet of the subscriber. This creates an opportunity for great improvements in cost and performance for short distance communication links. A technique for low-power digital communication over short transmission lines that exploits this possibility is described. The typical power is more than an order of magnitude lower than the power required with conventional circuits. Associated with this technique are a tenfold reduction in the chip area occupied by the transmission line drivers and the elimination of coupling transformers. The power and chip-area reductions result from terminating and maintaining an open circuit at the receiver. These advantages make this line-driving technique particularly suitable for single-chip VLSI systems     

Implementation of digital filtering algorithms using pipelined vector processors

The implementation of digital filtering algorithms using pipelined vector processors is investigated. Modeling of vector processors and vectorization methods are explained, and then the performances of several implementation methods are evaluated based on the model. Vector processor implementation of FIR filtering algorithms using the outer product method and the indirect convolution method is evaluated. Recursive and adaptive filtering algorithms, which lead to dependency problems in direct vector processor implementations, are implemented very efficiently using a newly developed vectorization method. The proposed method computes multiple output samples at a time, making the vector length independent of the filter order. Illustrative examples comparing theoretical results with Cray X-MP simulation results are included.     

Three-dimensional image reconstruction by digital tomo-synthesis using inverse filtering

Conventional X-ray tomosynthesis with film can provide a sagittal slice image with a single scan. This technique has the advantage of enabling reconstruction of a sagittal slice which is difficult to obtain from the X-ray CT system. However, only an image on the focal plane is obtained by a single scan. Furthermore, the image is degraded by superimpositions of the structures outside of the focal plane. A new three-dimensional image reconstruction method is proposed. This method utilizes a three-dimensional convolution process with an inverse filter function which is derived analytically by the point spread function of the projection and backprojection geometry. A digital tomosynthesis system has also been constructed for the purpose of evaluating the proposed method. This system was used in phantom experiments and clinical evaluations, and it was confirmed that the proposed method was able to reconstruct a better three-dimensional image with less artifacts from outside of the focused slice.     

Online digital filtering

The advantages of the recursive digital filter as a real-time signal processor are stated, and, as an example, a fourth-order Cheby?shev lowpass filter has been synthetised and programmed into an online computer. Typical responses are shown for pulse, step and low-frequency mixed sinusoidal signals.     

Fault-tolerant digital filtering architectures using fast finite field transforms

Digital filtering architectures for highly parallel realizations containing distributed error control are presented. They involve the interconnection of fault-tolerant sections using finite field arithmetic into which powerful cyclic error-correcting codes can be imbedded naturally. Realizations employing finite field transform domains and new techniques for protecting the transform coefficients are developed. These coefficients' special property, called the Chord Property, permits error detection and correction in the transform domain, and the proper selection of certain code parameters can expand this capability. Fast Transform algorithms with distributed error-control are possible because the interstage variables also obey limited chord properties. The interplay between these properties and certain code parameters are used to eliminate undesirable error propogation and provide reliable digital filter realizations.     

Two-dimensional digital filtering

The problems of designing and implementing LSI systems for the processing of 2-D digital data, such as images or geophone arrays, are reviewed and discussed. This discussion encompasses both FIR and IIR digital filters and with respect to the latter, the issues of stability testing and filter stabilization are also considered. Techniques are also presented whereby such filtering can be accomplished using either 1 or 2-D LSI systems.     

数字语音解码器的低功耗设计策略

主要从系统级、算法级、结构级等多个层面综合考虑减少数字语音解码器的功耗.系统级使用双向不交叠时钟技术,在提高耗时长的模块运算频率的同时消除了电路的竞争与冒险;算法级主要使用汇编语言重写和优化原代码,既可以压缩源代码,更能充分挖掘硬件的运算潜力;在结构级,主要利用并行技术,增加协处理器进行并行计算,有效提高运算速度.另外在布局布线时使用全定制集成电路设计技术手工布线,大为减少解码器的芯片面积.     

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead     

Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm ². The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns     

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

Improved approximate QR-LS algorithms for adaptive filtering

This paper studies a class of O(N) approximate QR-based least squares (A-QR-LS) algorithm recently proposed by Liu in 1995. It is shown that the A-QR-LS algorithm is equivalent to a normalized LMS algorithm with time-varying stepsizes and element-wise normalization of the input signal vector. It reduces to the QR-LMS algorithm proposed by Liu et al. in 1998, when all the normalization constants are chosen as the Euclidean norm of the input signal vector. An improved transform-domain approximate QR-LS (TA-QR-LS) algorithm, where the input signal vector is first approximately decorrelated by some unitary transformations before the normalization, is proposed to improve its convergence for highly correlated signals. The mean weight vectors of the algorithms are shown to converge to the optimal Wiener solution if the weighting factor w of the algorithm is chosen between 0 and 1. New Givens rotations-based algorithms for the A-QR-LS, TA-QR-LS, and the QR-LMS algorithms are proposed to reduce their arithmetic complexities. This reduces the arithmetic complexity by a factor of 2, and allows square root-free versions of the algorithms be developed. The performances of the various algorithms are evaluated through computer simulation of a system identification problem and an acoustic echo canceller.