Component reduced all-pass filter with a grounded capacitor and high-impedance input

In the literature, opportunities of the current conveyors with reduced current gains are not adequately emphasised for filter designs. In this study, we show a new all-pass filter (APF) possibility using a current conveyor with half current gain. Although many first-order voltage mode APFs were proposed, most of them either cannot provide high input impedance and grounded capacitor features together or they provide these features with components more than necessary. The presented circuit provides both of these features using reduced number of elements. Spice simulation and experimental results are given to verify the theoretical results.     

Single MIMO-OTA and single-grounded-capacitor-based first-order allpass filter design

A novel first-order voltage-mode allpass (AP) filter employing a single multiple-input-multiple-output operational-transconductance-amplifier (MIMO-OTA) and a single grounded capacitor is introduced in this article. Compared to the corresponding already published topologies, the offered benefits are as follows: it employs minimum number of active and passive components; the only capacitor is grounded, which is good for a monolithic integration of an IC; and the absence of any matching condition for its realisability. The performance of the proposed circuit has been evaluated through simulation results, utilising the analogue design environment of Cadence software.     

First-order allpass filter using multi-input OTA

A novel first-order allpass filter, operating in voltage-mode, is introduced in this article. Compared with the corresponding already proposed structures, attractive offered benefits are the capability for simultaneous offering a minimum number of active and passive components, and the absence of any realisability restriction. These have been achieved by employing a multiple-input operational transconductance amplifier as active element. The performance of the proposed circuits has been evaluated through simulation results, utilising the Analog Design Environment of Cadence software.     

10 μA Quiescent Current Opamp Design for LCD Driver ICs

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of 10 A quiescent current opamp.     

A fast final adder for a 54-bit parallel multiplier for DSP application

A novel redundant binary-to-natural binary converter circuit is proposed which is used in the final addition stage of parallel multipliers. Use of this circuit in the final adder stage proves to be 17% faster than carry-look-ahead implementation. We used this algorithm in such a way that no redundant binary adder is required in compressing partial product rows. Only the natural 4:2 compressor circuits are used.     

具有高频补偿的CMOS MOCCII

为了使MOCCII(多端输出的第二代电流传输器)能工作于高频段,本文提出了一种具有高频补偿的CMOS MOCCII电路.对于电流传输函数I_Z/I_X及,I_(Z-)/I_X采用在电流镜中加一个可调电阻方法,使得电流镜的传输函数由一阶系统变成可调极点的二阶系统,调节电阻大小,使得极点远离S平面原点,从而提高电流镜频带宽度.对于电压传递函数V_X/V_Y,在X与Y之间加并行差分对,以增加等效跨导,提高V_X/V_Y的频带宽度,同时,在X与Y之间的负载电流镜中加入一个电阻,以进一步提高VX/VY的频带宽度.仿真表明,V_X/V_Y的-3dB截止频率由补偿前的544MHz提高到补偿后的1.053GHz;I_Z/I_X及I_(Z-)/I_X的-3dB截止频率分别由补偿前的510MHz、400MHz提高到补偿后的1GHz.最后,作为应用,给出了由补偿前后MOCCII所构成的电流模式滤波器.     

Lumped-element analysis and design of CMOS distributed amplifiers with image impedance termination

This paper presents a systematic matrix-based lumped-element analysis of CMOS distributed amplifiers (DAs). Since transmission lines (TLs) of the DAs are artificially constructed from a ladder of a finite number of inductors and capacitors, the conventional TL-based analysis of microwave DAs can not be accurately applied to CMOS DAs. The proposed lumped-analysis method is also more intuitive for analog circuit designers than the TL analysis adapted from microwave amplifiers analysis because it provides the performance characteristics of the amplifiers as functions of circuit elements values, and not the TL characteristics. The image impedance technique is used for the design of input/output terminating networks. A new image impudence matrix is defined to accommodate the extension of the theory from two- to four-port networks, and a practical realization of the image impedance matrix is presented using the available circuit elements in CMOS technology. The simulation results clearly indicate an improved voltage gain and a better gain uniformity over the bandwidth of the proposed DA design terminated at its image impedance compared with the amplifier terminated at its nominal TL characteristics impedance.     

Analog IC-Achievable Lineariser for Power Amplifiers Based on Adaptive Feedforward

A compensation technique for the amplitude and phase imbalances of a feedforward lineariser using the LMS algorithm, implemented entirely in the analog domain, is presented. The lineariser is suited to RF power amplifiers, and maybe entirely developed with analog IC technologies. From simulated two-tone tests, the circuit leads to an intermodulation (IMD) reduction superior to 35 dB for a 64-QAM signal, being cheaper and competitive in performance with usual DSP-based adaptation circuits. Different implementations are evaluated, and the application of the circuit to RF power amplifiers in the DVB-T and in the LMDS frequency bands is considered.     

基于部分积优化的高速并行乘法器实现

提出了部分积产生与压缩单元的改进结构,通过对部分积产生算法进行优化,采用选择器结构来替换传统的与或门,提高了部分积电路的性能,并降低了该模块的面积与功耗.对压缩单元的优化提高了部分积压缩的速度.对16×16并行乘法器综合验证表明,改进的乘法器性能提高14.5%,面积减少7.1%,同时功耗下降17.2%.     

Wideband MOSFET differential V/I converter

This article presents a proposed modified flipped voltage follower for applications in a wideband MOSFET differential V/I converter using IBM 0.13 μm technology. Operating with ±2.5 V supply rails, the transconductance is nominally 3.3 mS for an input differential signal voltage range of 0.5 V, and the ?3 dB bandwidth exceeds 4 GHz. The THD measured at 1 MHz for a differential input signal of 500 mVp-p is less than –82 dB, and is still below –50 dB at 1 GHz.     

Gap-coupled microstrip array antenna for wide-band operation

The theoretical and experimental investigations carried out on a gap-coupled microstrip array antenna reveal that there is a significant improvement in VSWR and bandwidth characteristics of the gap-coupled microstrip array antenna as compared with a conventional microstrip array antenna. The input impedance and the resonant frequency of the gap-coupled patch are found to depend heavily on the gap length as well as on the dielectric constant of the substrate material.     

DSP-based control of a high frequency three cell flying capacitor inverter

The design, instrumentation and early operation results of a digitally controlled voltage source inverter (VSI) are described. This inverter has been structured from a three cell flying capacitor inverter (TCFCI). Two different inverter control modes – open-loop and closed-loop – are applied by a digital system based on a Texas Instrument TMS320C6713 digital signal processor (DSP) board. The VSI is able to generate AC voltage signals up to 120 V amplitudes at a maximal 6 A current, from ～9 kHz to ～60 kHz in ～900 Hz steps in both controls by varying the signal period through the square-wave command strategy. The multi-cell structure of the inverter provides an output frequency nearly three times that of the TCFCI semiconductor commutation. The power output of the TCFCI can drive a high frequency step-up transformer which, in turn, is associated with a cylindrical reactor where dielectric barrier discharges (DBD) are conducted.     

Design and implementation of sensorless techniques for switched reluctance drive systems

This article proposes two different methods for estimating the shaft position for a switched reluctance motor (SRM). Method 1 uses the self-inductance estimation technique to obtain the rotor position. First, by on-line measuring the slope of the stator current and compensating for the back electromotive force (EMF) effect, the self-inductance of the SRM can be detected. Then, the shaft position of the motor can be estimated according to the self-inductance. Method 2, on the other hand, uses the phase-locked loop technique to generate high-frequency signals. These signals can be used to estimate the shaft position of the SRM. The two proposed methods are compared and discussed in the article. Several experimental results are shown to validate the theoretical analysis. The adjustable speed range of the system is from 10 to 3000 rpm. Additionally, the proposed drive system can automatically start from a standstill to a setting speed.     

基于动态相位调整算法的高速采样系统设计

高速采样技术在雷达信号处理系统中至关重要。在使用多通道串行输出AD芯片进行采样时,AD芯片输出的时钟信号与串行数据信号在传输的过程中获得了不同程度的延时,导致关键路径的时序要求不能够得到满足。为了解决上述问题,提出了一种自适应动态相位调整算法,动态调整时钟和数据的相位关系使其能够在高速条件下正确匹配;设计了基于ADS6445模数转换芯片和Virtex-5 FPGA芯片的采样系统对算法进行验证,经系统测试该算法成功将时钟变化沿对准了数据窗中心位置,大幅度提高了系统采样的准确性和稳定性。经计算,系统的采样数据有效位达到11位以上,满足雷达信号处理对数据精度的高要求。     

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

h active area of 2.0 × 2.5 mm2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.     

High-efficiency bipolar transconductors composed of hyperbolic function circuits with an intermediate voltage terminal and a triple-tail cell

Relatively high transconductance in bipolar devices contributes to the economy of power dissipation on analog integrated circuits. Recently, a high-speed transistor, such as the HBT attracts attention of researchers and developers in electronic communication industries and is expected to be applied to RF circuits. In this paper, high-efficiency bipolar transconductors are presented. The proposed circuits are composed of a hyperbolic function circuit with an intermediate voltage terminal and a triple-tail cell. The parameter values for linearisation are all integers. The values can be realised precisely. The linearity of the proposed transconductors is superior to the triple-tail cell. The linear input range is 1.5 times as wide as that of the conventional triple-tail cell. Nevertheless, the power dissipation is lower than the triple-tail cell. Further, sensitivity analysis shows that the proposed transconductors have lower sensitivity than the triple-tail cell. These properties are confirmed by SPICE simulation.     

基于非线性DAC的高速直接数字频率合成器

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.     

超宽带低相噪频率合成器的实现

介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。     

X波段低相噪宽频带雷达频率综合器设计

随着雷达导引头在弹载方面的广泛应用,导引头的抗电子干扰能力成为一项关键技术。雷达频率综合器作为雷达系统的核心部件,其产生本振信号的质量对雷达系统的抗电子干扰能力具有决定性影响,这对本振信号的跳频带宽、相位噪声、杂波抑制度、平坦度等参数指标提出了更高的要求。本文运用直接数字频率合成(DDS)技术和先进设计系统(ADS)仿真技术进行宽带阻抗匹配,采取有效信号串扰隔离技术,使雷达频率综合器的X波段本振信号的各项指标得到明显改善。通过实验测试,本振信号可以实现快速跳频,跳频带宽达到500 MHz,提高了雷达的抗干扰能力;相位噪声优于-98 dBc/Hz@1 kHz,有效改善了雷达导引头的接收灵敏度。     

Universal filters of arbitrary order and type employing square-root-domain technique

Novel Single Input Multiple Output (SIMO) and Multiple Input Single Output (MISO) universal filter topologies of arbitrary order and type are introduced in this paper. The proposed topologies have been realised by employing Square-Root Domain (SRD) technique. An offered benefit of the universal filter topologies is that only grounded capacitors are required for their implementations and the resonant frequency of the filters can be electronically controlled by an appropriate dc current. The proposed universal filters simultaneously offer all the five standard filtering functions i.e. Lowpass (LP), Highpass (HP) and Bandpass (BP), Bandstop (BS) and Allpass (AP) frequency responses. In addition, the SIMO topology is generic in the sense that it can yield four different stable filter configurations. Two design examples are provided in each configuration and the correct operation of the corresponding topologies has been evaluated through the PSPICE software with BSIM 0.35-µm CMOS process model parameters.