一种带宽为3.8GHz，增益步长为0.1dB的可编程增益放大器

A broadband programmable gain amplifier（PGA） with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB (-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.     

增益带宽可调放大器

本论文介绍一款高指标的增益带宽可调放大器的设计与制作。设计采用多重措施来降低噪声，提高效率，并且采用负反馈思想抑制零点漂移。实测表明，设计出的增益带宽可调放大器各项指标能很好地达到设计要求，具有一定的实用性，为工业生产和电子竞赛提供可靠参考。     

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning...     

一种新颖的可应用于多模多频接收机可配置的可变增益放大器

本文阐述了一种新颖的可应用于多模多频接收机射频前端可配置的可变增益放大器的设计方法。可变增益放大器包括增益放大电路,控制电路,直流失调消除电路和模式转换电路四个部分。这种结构可以在保证多模多频应用的前提下通过硬件复用最大化来节省芯片面积和功耗。电路采用0.18 um CMOS 工艺,在1.8V的供电电压下可实现5dB 至87dB的动态范围,电路的带宽（所有增益下）大于80 MHz。此外,直流失调消除电路有效抑制了直流失调成分至小于40mV。整个电路的功耗小于3mA,面积为705um*100um。     

一种用于接收机的低功耗自动增益控制环路

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).     

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while oper...     

Low-voltage low-power 100 MHz programmable gain amplifier in 0.35 μm CMOS

This paper presents a low-voltage low-power intermediate-frequency programmable gain amplifier (PGA). To achieve low-voltage low-power and wideband operation while preserving linearity, the proposed cell is based on a very simple g _m -boosted differential pair degenerated with a hybrid polysilicon-MOS programmable resistor structure. Fabricated in a 0.35 μm CMOS technology, the PGA consumes less than 0.5 mW at a single 1.8 V supply. Measured results for a 3-bit implementation show a 0 to 18 dB linear-in-dB programmable gain with a constant bandwidth of 100 MHz when driving 150 fF capacitive loads. Distortion levels are below −72 dB over the whole gain range at 10 MHz for a 0.2 V _{p − p} differential output. Compared with other previously reported designs, it shows a good trade-off when all PGA parameters are considered.     

一种低压、恒增益Rail-to-rail运算放大器的设计

文章设计了一种低压、恒定增益、Rail-to-rail的CMOS运算放大器。该放大器采用直接交迭工作区的互补并联输入对作为输入级,在2V单电源下,负载电容为25pF时,静态功耗为0.9mW,直流开环增益、单位增益带宽、相位裕度分别为74dB、2.7MHz、60°。     

Electronically tunable high gain current-mode instrumentation amplifier

A new design for electronically tunable current mode (CM) instrumentation amplifier (IA) is presented in this paper. It employs Modified Z copy Current Differencing Transconductance Amplifier (MZC-CDTA) along with a resistor. The gain of the proposed CM IA is controlled by a single resistor and can theoretically approach infinite value. Electronic tuning feature is augmented by using a MOS based resistor. The functionality is verified through simulations on Cadence Virtuoso using TowerJazz’s 180 nm Technology Node and performance against PVT variations is also examined. Feasibility of on-chip implementation is confirmed by the post-layout simulations carried out.     

具有30dB增益和1-16GHz带宽的CMOS低噪声中频放大器

This paper presents a high-gain wideband low-noise IF amplifier aimed for the ALMA front end system using 90-nm LP CMOS technology.A topology of three optimized cascading stages is proposed to achieve a flat and wideband gain.Incorporating an input inductor and a gate-inductive gain-peaking inductor,the active shunt feedback technique is employed to extend the matching bandwidth and optimize the noise figure.The circuit achieves a flat gain of 30.5 dB with 3 dB bandwidth of 1-16 GHz and a minimum noise figure of 3.76 dB.Under 1.2 V supply voltage,the proposed IF amplifier consumes 42 mW DC power.The chip die including pads takes up 0.53 mm~2,while the active area is only 0.022 mm~2.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.     

PIN二极管原理及其在射频增益控制放大器中的作用

文章主要介绍PIN二极管的原理及在射频增益控制放大器中的作用.     

Partial positive feedback for gain enhancement of low-power CMOS otas

Four circuit schemes that use partial positive feedback for gain enhancement in CMOS OTAs are examined. These circuit schemes are classified as type I and type II circuits. Type I circuits use a differential input pair with positive feedback and type II circuits use a active load with positive feedback. As the primary emphasis of these circuits is for micropower operation, the circuits have been examined in detail in the subthreshold region. A comparison of the primary characteristics of these circuits together with simulation results are presented. It is shown that partial positive feedback is a viable technique to increase the gain and the bandwidth of CMOS OTAs. Without any increase in power, a 20 dB increase in gain and a 5X improvement in bandwidth is feasible.     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

一种适用于0.8VCMOS助听器的电流模前馈增益控制系统

摘要：本文介绍了一种适用于助听器前端系统的电流模前馈增益控制系统。和传统自动增益控制系统相比,电流模前馈增益控制通过数字增益控制码来实现前端系统总谐波失真的显著降低。为了从麦克风微弱的输出信号中得到数字控制码, 本文提出了用电流模实现的整流电路和电流模状态控制电路.该设计基于0.13微米CMOS工艺. 测试表明芯片可工作于0.6V的电源电压.在电源电压为0.8V下, 输出摆幅500mVp-p的信号总谐波失真在0.06% (-64dB)以下, 且功耗控制在40uW以内.另外,系统的等效输入噪声达到4uVrms,最大增益保持在33dB.