A new characterization of sub-μm parallel multilevelinterconnects and experimental verification

This paper describes the generation of a new universal design chart for submicron multilevel interconnection and its verification using test-structures. This has been developed to give the precise interconnect-capacitance for parallel submicron multilevel interconnections. Parasitic effects of a passivation film (Si₃N₄) on the interconnect capacitance have been also studied. The results of the test-structures designed have shown an excellent agreement with the design-chart with a maximum error of 8%. Furthermore, a simple propagation delay and response voltage model to a step voltage input have been developed incorporating the parallel-interconnect capacitance model. The new model is based on a lossy-transmission line equation and demonstrates an excellent agreement with RC lumped circuit simulations, resulting in a new simple and accurate prediction method for interconnect delay for use in VLSI timing design     

The correlation between gate current and substrate current in 0.1μm NMOSFET's

The correlation between gate and substrate currents in NMOSFET's with effective channel length, L_eff, down to 0.1 μm is investigated within the general framework of the lucky-electron model. It Is found that the correlation coefficient, Φb/Φ_i, decreases with decreasing L_eff in the 0.1 μm regime, where Φ_b is the effective Si-SiO₂ barrier height for channel hot-electrons, and Φ_i is the effective threshold potential for impact ionization. Furthermore, this effect becomes stronger in NMOSFET's with shorter L_eff. These experimental results suggest the need for further investigation on specific assumptions in the lucky-electron model to understand hot-electron behavior and impact ionization-mechanisms in 0.1 μm-scale NMOSFET's     

An analytical model for self-limiting behavior of hot-carrierdegradation in 0.25 μm n-MOSFET's

Hot-carrier degradation of short-channel n-MOSFETs becomes saturated after reaching a certain threshold value. The physical mechanism for this self-limiting behavior is investigated. It is proposed that the hot-carrier-induced oxide trapped charge and interface states form a potential barrier that repels subsequent hot carriers from causing further damage and can lead to the saturation of device degradation. A physical model is developed on the basis of the analysis. The model is verified by experimental results and can be used for more accurate device reliability projection     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant     

On the properties of the gate and substrate current after softbreakdown in ultrathin oxide layers

In this work we have studied soft breakdown (SBD) in capacitors and nMOSFET's with 4.5-nm oxide thickness. It is shown that for larger area devices gate current and substrate current as a function of the gate voltage after SBD are stable and unique curves, but for smaller area devices both currents become lower and unstable. This difference can be explained by the different energy available for discharging in the SBD path. It is shown that the SBD detection strongly depends on the test structure area. In nMOSFET's for positive gate polarity, the large increase in the substrate current at the SBD moment is proposed as a sensitive SBD detector. Two level fluctuations in the gate current are investigated at different voltages and are explained by means of a model where electron capture-emission in the traps of the SBD path induces local field fluctuations causing variations in the tunneling rate across the oxide. In the substrate current directly correlated two-level fluctuations are observed     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

Gain coefficient, quantum efficiency, transparency current density,and internal loss of the AlGaAs-GaAs-based lasers on Si substrate

The AlGaAs-GaAs based lasers on Si substrate with GaAs quantum-well and island-like active regions are fabricated by metal-organic chemical vapor deposition. The parameters of internal quantum efficiency, gain coefficient, transparency current density, and the internal loss that describe the operating characteristics of laser diodes are investigated. The optical confinement factor is calculated with the assumption that the light emission occurs from the island regions only. In addition, longer minority carrier lifetime obtained for the lasers with island-like active regions reveals their improved characteristics over conventional quantum-well lasers     

A 1.6-μm pumped 1.9-μm thulium-doped fluoride fiber laser andamplifier of very high efficiency

Results are presented for color center, and semiconductor, laser pumping of the 1.82 μm transition in a thulium-doped fluoride fiber. As an amplifier small signal gain efficiencies of 8.1 dB/mN were attained with a maximum gain of 36.5 dB being achieved for around 17-18 mW of launched pump power. As a laser a maximum slope efficiency of 84% and a minimum threshold for oscillation of 330 μW was also demonstrated for this system. Furthermore by suppressing all reflections down to <36 dB superfluorescent or ASE output was observed. In achieving efficient operation with a diode laser pump source this system shows strong commercial potential     

A study of quantum interference fluctuations in deep sub-μmMOSFET's under cryogenic conditions

We investigated the phase coherence length, l_φ, in large Si-MOSFET's fabricated using current process technology, with a particular emphasis on highly doped silicon substrates, and then studied the effects of quantum conductance fluctuations in deep sub-μm MOSFET's, with channel length comparable to l_φ. We identified, in a 0.2 μm MOSFET, universal conductance fluctuations in the strong inversion regime and conductance fluctuations due to variable range hopping in the weak inversion regime. The drain bias dependence of these fluctuations indicates clearly that they become a serious concern only at drain voltages lower than 10 mV. Therefore, even if the wave nature of electrons results in quantum conductance fluctuations, it will not lead to a limitation on device miniaturization in future Si-ULSI's     

A 45-m telescope with a surface accuracy of 65 μm

The Nobeyama 45-m telescope has been upgraded for higher frequency and higher sensitivity observations. The surface accuracy of the antenna was improved from 0.2 mm rms to 65 μm rms using a radio holography method at the prime focus. Pointing accuracy was also improved by replacing a large Gregorian subreflector cabin with a smaller cassegrain subreflector in 1985 to reduce wind loading effects, and by installation of a new master collimator with multi-pole resolvers which were calibrated to an accuracy of 0.4 arcsec rms in 1988. Four SIS receivers using Nb/AlO_x/Nb array junctions are now available on the telescope for 40, 80, 100, and 150-GHz bands. These receivers achieved quite low noise and wide-band tunability. The 2×2 multi-beam receiver for 115 GHz is very powerful for mapping observations. These improvements of telescope performance and these receivers have significantly increased the astronomical observation capability of the telescope in the wide frequency range of 40 to 150 GHz     

Improving the bandwidth gain-independence and accuracy of the current feedback amplifier

A high-performance current feedback amplifier circuit referred to as an operational current feedback amplifier is described in this paper. The technique employed involves the incorporation of the input circuit of the current feedback amplifier in the feedback loop of an operational amplifier to reduce the input impedance at the inverting terminal of the current feedback amplifier. The new circuit possesses the gain accuracy and bandwidth of the current feedback amplifier but realizes significant improvement in bandwidth accuracy and bandwidth gain-independence. Experimentally, using AD844s, an order of magnitude reduction in bandwidth variation with changing gain was achieved in the noninverting configuration and almost complete bandwidth invariance was realized in the inverting configuration.     

Modeling of substrate current in p-MOSFET's

It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's. The impact ionization rate extracted for holes is found to be 8 × 10⁶exp (-3.7 × 10⁶/E), where E is the electric field. Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's. The hot-carrier-induced breakdown voltage is therefore also about two times larger.     

Temperature dependence of MOSFET substrate current

Hitherto, theoretical models for MOSFET substrate current predicted that substrate current is a strong function of temperature. However, experimental data presented in this and previous studies show that the ratio of substrate current to drain current is insensitive to temperature over the range 77 to 300 K. The authors propose a modified model for an electron mean-free path (MFP) in the substrate current based on the concept of energy relaxation. The different between the energy and momentum relaxation MFP is clarified, and it is shown that a substrate current model with modified MFP can explain the temperature dependence of the substrate current     

Detailed characterization and analysis of the breakdown voltage infully depleted SOI n-MOSFET's

The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 μm, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Estimate of substrate influence on space-charge-limited current

The Mott and Gurney law, which expresses the space-charge-limited current in intrinsic material, cannot be used for planar structures. An I/V curve is plotted for a quasi-intrinsic material. For a doped substrate, the I/V curve is simply displaced by ?V. In a planar structure, the s.c.l.c. between two n layers, across the p? substrate, can be lowered by biasing the substrate.     

Low-threshold current, high-efficiency 1.3-μm wavelengthaluminum-free InGaAsN-based quantum-well lasers

We demonstrate high-performance Al-free InGaAsN-GaAs-InGaP-based long-wavelength quantum-well (QW) lasers grown on GaAs substrates by gas-source molecular beam epitaxy using a RF plasma nitrogen source. Continuous wave (CW) operation of InGaAsN-GaAs QW lasers is demonstrated at λ=1.3 μm at a threshold current density of only J_TH =1.32 kA/cm². These narrow ridge (W=8.5 μm) lasers also exhibit an internal loss of only 3.1 cm^-1 and an internal efficiency of 60%. Also, a characteristic temperature of T₀=150 K from 10°C to 60°C was measured, representing a significant improvement over conventional λ=1.3 μm InGaAsP-InP lasers. Under pulsed operation, a record high maximum operating temperature of 125°C and output powers greater than 300 mW (pulsed) and 120 mW (CW) were also achieved     

2 GHz controlled current conveyor in standard 0.8 μm BiCMOStechnology

A new controlled current conveyor operating in class A and implemented using a low-cost industrial BiCMOS 0.8 μm process is described. Its electrical characteristics (voltage and current transfers, parasitic impedances) have been measured. With a bias current of 500 μA and supplied under ±2.2 V, the measurement results show that the circuit exhibits very large -3 dB bandwidths: from DC to 4.5 GHz for the voltage transfer (between Y and X) and from DC to 2 GHz for the current transfer (between X and Z)     

1.32-μm GaInNAs-GaAs laser with a low threshold current density

In this letter, we report on a recent development of diluted nitride laser diodes operating at the wavelengths around 1.3 μm. The lasers grown by molecular beam epitaxy and processed into 20-μm-wide ridge waveguide structures, mounted episides up on subcarriers, exhibit a threshold current density as low as 563 A/cm², slope efficiency of 0.2 W/A per facet, light power up to 40-mW continuous-wave, and characteristic temperature of 97-133 K     

Fully integrated 0.25 μm CMOS VCSEL driver with current peaking

A vertical-cavity-surface-emitting laser (VCSEL) driver chip based on a novel circuit concept for current peaking has been designed and fabricated in a 0.25 μm complementary metal-oxide-semiconductor (CMOS) process. This concept allows the easy integration of a peaking driving scheme in CMOS. Experimental results show speed extension from 500 Mbit/s for current on-off to 3.9 Gbit/s for current peaking driving