基于SOPC的微小型无人机容错飞行控制平台设计

针对微小型无人机的高可靠性和微型化要求,将可编程片上系统(SOPC)技术和容错技术相结合,设计出一套双余度容错飞行控制平台。从容错方案的选取到硬件和软件的实现给出了具体实施方案,并对同步技术、故障诊断与定位、动态重构与隔离等关键技术进行了研究。经过仿真验证和试验表明,该方案设计合理,系统平台不仅可以实现无人机飞行控制的基本功能,而且具有很高的集成度和灵活性,并且满足一次故障安全。     

基于FPGA延迟链差值的时间间隔测量方法

基于FPGA的时间间隔测量,由于其精度高、成本低、系统结构简单等突出优点,在时间间隔测量领域已成为主要研究方向之一。介绍了一种基于FPGA延迟链差值的时间间隔测量方法,利用片内单元缓冲器与触发器组成的延迟链形成的延迟链差值进行时间间隔测量,整个系统占用了较少的芯片资源。此方法既可为功能电路独立使用,也可通过FPGA中Logic Lock反标注进行系统的移植。此次研究建立在Altera公司的Cyclone系列二代芯片上,时序仿真表明时间间隔测量误差小于1ns,硬件测试精度优于2ns。     

Realizing reliable logic and memory function with noise-assisted Schmitt trigger circuits

Schmitt trigger is a comparator circuit with hysteresis, implemented by applying positive feedback to a noninverting input. Recently, it has been verified that noise under certain condition can help nonlinear circuit to realize reliable logical stochastic resonance (LSR). In this letter, we demonstrate that, without any modifications, Schmitt trigger can operate flexibly both as logic operation and latch operation in an optimal noise range. In traditional Schmitt trigger, the hysteresis is designed for resisting noise. In the new design, the hysteresis tends to enhance the LSR effect in Schmitt trigger with the help of noise and helps the system to perform better at higher noise levels. Thus, our results extend the application scope and generality of the traditional Schmitt trigger.     

不同评价函数下阵列天线自修复分析

由大量阵元组成的阵列天线其性能受不断出现的失效阵元影响,可通过进化重配置阵列中剩余正常阵元激励实现性能修复。分析了阵列天线进化重配置过程,综合分析了自修复过程中评价函数类型,设计了不同评价函数分析流程,通过Chebyshev直线阵的自修复仿真实验,分析了不同评价函数对阵列天线自修复结果的影响,分析结果表明,基于性能参数的评价函数和方向图匹配与性能参数相结合评价函数具有较好性能,该分析结果为具有失效阵元的阵列天线自修复中评价函数选择提供了参考。     

EAST装置电子回旋共振加热系统中央控制器设计

介绍了基于可编程逻辑门阵列(FPGA)芯片的电子回旋共振加热(ECRH)系统中央控制器的设计,阐述了中央控制器对输入的总控触发信号、等离子体电流信号、ECRH系统状态信号、高压输出状态信号、波输出状态信号、各类停止信号以及各输出控制信号等的处理与控制逻辑.对FPGA程序做了时序仿真,仿真结果表明,该控制器能够实时响应总...     

Gold Nanoparticles‐Based DNA Logic Gate for miRNA Inputs Analysis Coupling Strand Displacement Reaction and Hybridization Chain Reaction

The molecular level DNA logic gates assisted by nanomaterials hold great promise for disease diagnosis applications. However, designing convenient and sensitive logic gates for molecular diagnostics still remains challenging. In this work, a DNA logic gate platform for miRNA inputs analysis based on the observation of localized surface plasmon resonance variation of gold nanoparticles (AuNPs) is fabricated. As a demonstration, two biomarkers to differentiate indolent and aggressive forms of prostate cancer, miR‐200c and miR‐605, are selected as examples of logical inputs. In addition, five DNA probes are designed according to strand displacement reaction and hybridization chain reaction which are required for DNA logical operation. Since target miRNA inputs are able to trigger DNA structural transformations, which are further used to precisely regulate salt‐induced AuNPs aggregation, miRNA inputs information can be converted to the information of AuNPs states as outputs. This developed system performs amplified detection of low‐abundant target miRNAs without the requirement of any enzymes. In addition, single base‐pair mismatched miRNAs can be effectively differentiated. High‐order logic gates can also be developed with further modifications. Therefore, the DNA AND logic gate is successfully constructed with flexible operations, which has potential in biochemical study and disease diagnosis.     

强流质子加速器PXIe控制器的子控制系统

针对一台用于加速器驱动次临界系统(ADS)的强流质子加速器,即ADS注入器Ⅱ,开展其定时系统和快保护系统的研究工作,设计了一款可在这两个系统中应用的PXIe控制器。该控制器基于现场可编程门阵列设计,可实现光纤通信、PXIe总线通信、延时触发信号输出等功能。其中,光纤通信功能用于实现各PXIe控制器之间的数据传输;PXIe总线通信功能主要是为了实现控制器与工控机之间的数据交互;延时触发信号输出功能可以给出精确的低电压晶体管-晶体管逻辑电平标准的时序触发信号,从而保证加速器的各子系统和设备能够按照一定的时序协调一致地工作。     

用于弹道测量的实时测速同步触发仪设计

介绍了一种实时获取当发弹丸速度的同步触发系统.采用两台天幕靶和测时电路实时测量当发弹丸的速度,根据测得的速度和事先确定的靶距,计算输出测试仪器触发需要的延时值.同时,设计了滤除蚊虫、飞鸟等外界环境干扰的电路,确保输出的触发信号稳定可靠.详细介绍了系统组成、工作原理与逻辑电路的设计.设计的系统经过实弹射击试验验证,工作稳...     

基于FPGA技术的加速器切束控制系统设计

针对加速器驱动次临界系统(ADS)中强流质子直线加速器,即ADS注入器Ⅱ,设计了采用现场可编程门阵列(FPGA)切束技术的加速器快保护控制系统。当系统检测到束流异常故障信号时能快速切断束流,并上传故障信息,方便故障排查和后期数据分析。该控制器基于FPGA设计,可实现光纤通信、串口通信、逻辑电平信号输出等功能。其中,光纤通信功能用于控制斩波器电源快速切断束流;串口通信用于实时传输设备状态信息;逻辑电平信号输出用于控制继电器产生开关量信号去远程控制保护设备,以防止运行设备的损害。通过现场运行测试,切束响应时间在10 s之内,达到安全设计要求。     

激光触发变压器型螺旋脉冲调制器的同步控制

 建立了精确的激光触发变压器型脉冲调制器的同步触发系统。分别对脉冲调制器初级电脉冲触发控制信号与电脉冲输出时刻之间、变压器充电起始时刻与激光器Q开关触发信号之间、激光信号与脉冲调制器放电时刻之间的延时进行了测量,并分析其相互间时序关系;通过对变压器输出电压信号进行采样滤波后,利用比较器输出逻辑门电路（TTL）信号作为激光器Q开关触发信号,实现了脉冲形成线充电时间与激光触发主开关放电过程的同步控制。开展了激光触发脉冲功率调制器主开关的实验研究,在形成线充电电压-590 kV时,在假负载上得到-305 kV,20 kA的电脉冲,脉冲宽度126 ns,激光到达主开关时刻与开关导通时刻间延时35 ns。     

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采用增量式PID控制算法和基于FPGA的相移数字触发器组成的励磁反馈控制系统实现对HL-2A装置脉冲发电机输出的控制,并通过基于西门子PLC构成的逻辑控制系统保护励磁系统的安全。实际运行结果表明,该励磁控制系统具有控制精度高、运行稳定可靠的优点。     

ACTIVE IMPACT CONTROL SYSTEM DESIGN WITH A HYDRAULIC DAMPER

We propose a new active impact control (or absorber) system that is able to respond to a highly rapid impact and a large flow rate. The system has advantage over a passive system regarding a feasible pressure and displacement regulation. The impact control system constructs both internal and external dampers, that is its orifice is placed inside and outside the hydraulic cylinder. The designed system has a set of logic valves, which respond rapidly to an external impact and are capable of discharging an instant excessive hydraulic flow, and a servo valve to control the pilot chamber of the logic valve. The impact control system is designed and fabricated based on an appropriate mathematical modelling and its dynamic analysis, and on various control performances. The control performance is verified by simulations and experiments.     

一种便携式冲击波超压测试系统

针对现在军用和民用对爆破的测量需求,提出了一种基于现场可编程逻辑门阵列FPGA和ICP传感器的便携式冲击波超压测试系统。测试系统主要以FPGA为主控芯片,采用ICP压电传感器,包含信号放大调理电路,AD转换电路,存储器模块以及工作状态显示电路。系统具有光触发、节点互触发和多节点同步触发等多种触发方式,连续重触发功能,以及多次采集时FLASH分块存储功能。系统上位机是以VC++为开发工具设计的软件,用于对数据进行分析、处理和显示。实验结果表明系统工作可靠,操作简便,能够实现对爆破冲击波超压的测试。     

相控阵天线内部通信的CAN控制器IP核设计

为实现相控阵天线波控系统小型化、芯片化的目的,设计了一种基于Avalon总线的CAN控制器IP核。参照CAN2.0B协议规范,给出了CAN控制器IP核的功能结构,利用Verilog硬件描述语言完成了控制器接口逻辑、位流处理器、位时序逻辑等模块设计,并进行了设备驱动及应用软件开发。将设计的CAN控制器IP核、Nios II微处理器、多个单元相位控制器IP核等集成到FPGA中构成子阵级波束控制的SoPC系统。最后对CAN总线的通信性能进行了实验测试。结果表明:设计的CAN控制器IP核能够在实际CAN网络中稳定可靠地收发数据。基于这种方式构建的系统,扩展方便、可移植性高、具有较强的适应性,也可用于高密度、紧凑型工业控制领域。     

Fast frequency modulation optical code division multiple access communication system

An optical fast frequency modulation code division multiple access communication system is proposed. In this system, an electrically controlled tunable optical filter (TOF) is used to encode the modulated broadband light source. The code depends on the function set to the controller. Two-dimensional code named functional code is also proposed based on a shifted sine function. The function defines the dynamic coding pattern of the central wavelength of the transmitted narrowband optical signal. Thus, the system will allow for an easy reconfiguration of the transmitter without the need for sophisticated encoder. At the receiver, a synchronized TOF with the same function is used as a decoder. The performance of this system is shown to be better compared with a fast frequency hopping and a spectral amplitude coding systems.     

Beam transport experiment with a new kicker control system on the HIRFL

A kicker control system is used for beam extraction and injection between two cooling storage rings(CSRs) at the Heavy Ion Research Facility in Lanzhou(HIRFL). To meet the requirements of special physics experiments, the kicker controller has been upgraded, with a new controller designed based on ARM+DSP+FPGA technology and monolithic circuit architecture, which can achieve a precision time delay of 2.5 ns. In September2014, the new kicker control system was installed in the kicker field, and the test experiment using the system was completed. In addition, a pre-trigger signal was provided by the controller, which was designed to synchronize the beam diagnostic system and physics experiments. Experimental results indicate that the phenomena of "missed kick"and "inefficient kick" were not observed, and the multichannel trigger signal delay could be adjusted individually for kick power supplies in digitization; thus, the beam transport efficiency was improved compared with that of the original system. The fast extraction and injection experiment was successfully completed based on the new kicker control systems for HIRFL.     

基于VxWorks的水下机器人通信系统设计

针对水下机器人（ROV）在深海高噪声干扰环境中工作的特点,设计了一套基于VxWorks实时操作系统的ROV整体通信系统,实现了水下核心控制器对水下分系统快速高效的信息采集和数据分配,水下系统和水面控制器稳定实时的数据交换;硬件方面设计了以CAN总线为基础的水下通信系统,通过FPGA实现了CAN总线和PC104总线之间的时序逻辑转换,软件方面设计了基于TCP/IP协议栈的水面操控台和ROV之间的网络通信方式和水下各系统之间的CAN总线通信方式,着重介绍了基于缓冲队列的网络通信编程;通信系统数据测试实验表明：CAN总线通信和网络通信均具有良好的实时性和可靠性,满足最初的设计需求,而且采用模块化设计,便于维护和移植。     

A hardware fast tracker for the ATLAS trigger

The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10³⁴ cm^–2 s^–1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.     

三脉冲功率系统模块

采用基于并联Blumlein脉冲形成线的MHz重复频率脉冲功率技术和基于激光触发气体开关的多级触发系统,设计了脉冲功率系统模块,该模块具备6路输出能力,每路均可以MHz重复频率猝发方式输出三脉冲,幅度可达300 kV。对模块中的Blumlein装置、脉冲汇流、隔离网络、触发系统等部件参数进行了设计。以多脉冲直线感应加速器感应腔作为负载,对该模块的性能进行了分析,结果表明:模块中每个脉冲的输出时间抖动小于2.3 ns（标准差）,脉冲间最小时间间隔大于500 ns时可在负载上获得高品质波形。     

全钒液流电池充放电测试系统设计

针对以太网技术在高速图像传输中常见的带宽利用率低,传输协议受限的问题,设计了一种基于可编程逻辑器件FPGA实现千兆以太网传输系统的方案,分析了基于IEEE802.3标准的以太网帧格式和循环冗余校验(CRC),实现了MAC数据包的封装和PHY芯片88E1111的配置,完成了千兆网络系统的设计和高速数据的传输。结果表明,该方案具有成本低,传输速率快且传输协议不受限制的优势,并最终成功应用于某水下高速图像传输系统中。