65 nm CMOS SSB mixer for UWB synthesiser

The present work addresses the design of a 65 nm CMOS wide-band single-sideband mixer for UWB synthesiser. The circuit has been designed inductorless and with few capacitors, in order to save silicon area and, at the same time, to get a mixer independent of the adopted frequency plan and synthesiser architecture. Particular attention has been paid to reducing the spurs as much as possible. In order to address a realistic investigation, the design has accounted also for the corner cases and the possible impairments in the input signals. A comparison with the state-of-the-art of the SSB mixers shows the low power consumption of the present work.     

用于802.11a的5.5GHz低噪声正交混频器的设计

设计了一种新的工作在5．5GHz的低噪声正交混频器。为了减少传统Gilbert正交混频器中的噪声，使用了一个电感来抵消寄生电容对于噪声系数的影响。经过仿真在1．8V电压下，当本振（LO）、射频（RF）和中频（IF）的频率分别为5．51GHz，5．5GHz和10MHz的情况下，单边带噪声系数（SSBNF）可以低至8．33dB，三阶输入截至点（ⅡP3）为2．88dBm，功耗为14．4mW。     

应用于IMT-A与UWB系统的高线性度双频带混频器

The design and analysis of a reconfigurable dual-band down-conversion mixer for IMT-advanced(3.4–3.6 GHz) and UWB(4.2–4.8 GHz) applications are presented.Based on a folded double-balanced Gilbert cell,which is well known for its low voltage,simplicity and well balanced performance,the mixer adopts a capacitive cross-coupling technique for input matching and performance improvement.Switched capacitors and resistors are added to shift the working bands.Fabricated in a TSMC 0.13 m process,the test results show flat conversion gains from 9.6 to 10.3 d B on the IMT-A band and from 9.7 to 10.4 d B on the UWB band,with a noise figure of about 15 d B on both bands.The input third-order intercept points(IIP3) are about 7.3 d Bm on both of the frequency bands.The whole chip consumes 11 m W under 1.2 V supply and the total area of the layout is 0.760.65 mm2.     

基于DC-OFDM的C-WPAN UWB物理层硬件实现

文章实现了一种基于双载波正交频分复用的超宽带物理层（射频前端以及基带处理器）,适用于C-WPANUWB标准。所实现的UWB物理层支持从53.2-480Mbit/s的数据率,并且在CM1、CM2和CM4的多径衰落信道、加性高斯白噪声、载波频率偏差和采样频率偏差高达50ppm的条件下达到8%的误包率。整个物理层包括一个工作在频带组2的射频收发机、一个6bit折叠内插结构的模数转换器、一个8bit电流舵的数模转换器以及一个数字基带处理器。前端电路的制造采用0.13μmCMOS工艺,数字基带处理器在Xilinx Vertex-5FPGA平台上实现。     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

Energy consumption of the IEEE Std 802.15.3 MAC protocol in communication link set-up over UWB radio technology

This paper examines the overhead associated with the IEEE Std 802.15.3 medium access control (MAC) protocol when used in conjunction with Ultra Wide-Band (UWB) radio technology. Particular features of the protocol examined include establishing, modifying and terminating data streams. The main focus of the paper is to investigate the overhead introduced in terms of energy consumption to manage the communication links. One of the main UWB technology candidates, Impulse-Radio (IR-UWB), utilizes very short time domain pulses which are low power and difficult to detect. This raises the question of how to design an efficient MAC protocol to harness the potential of the physical layer (PHY). For high data rate WPAN applications, the IEEE Std 802.15.3 protocol has been proposed as a suitable MAC. In the simulations the data source rate and the number of devices in the network are varied and the considerable overhead produced by command frames is observed.     

一种基于信道缩短的MB-OFDM UWB稀疏信道估计算法

在MB-OFDMUWB系统中,利用UWB信道的稀疏簇特性,提出一种基于信道缩短的MB-UWB稀疏信道估计算法。首先利用信道缩短滤波器来消除由于循环前缀长度不足造成信道间干扰和码间干扰,然后基于信道缩短后的接收信号,利用UWB信道的稀疏性,探测出非零值抽头的位置,避免了无谓的零值抽头估计,改善了算法的性能。仿真结果表明:当循环前缀CP长度小于信道长度时,LS算法和DFT算法逐渐失效,而新算法可以获得较好的估计性能。     

多带OFDM超宽带系统高性能分组检测器设计

针对多带OFDM超宽带（MB-OFDM UWB）系统,依据其物理层国际标准ECMA-368,提出了一种高性能的分组检测器。在改进传统互相关算法的基础上,通过累积多径能量,该分组检测器可以同时实现分组检测和符号精定时。仿真结果表明,与已有的分组检测算法相比,新方法具有更低的分组检测错误概率,同时也改善了符号精定时的准确度。     

基于导频序列信道缩短的超宽带信道估计

针对多频带超宽带系统,提出一种基于导频序列信道缩短的信道估计方法,解决了循环前缀长度小于信道最大多径延迟时难于估计信道参数的问题。首先在发送信号中插入块状导频,利用最小均方误差准则（MMSE）,在接收机前端设计信道缩短均衡器,然后根据均衡器输出序列估计出复合信道,最后通过反卷积解出原信道参数。仿真实验表明：该算法具有良好性能。     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

UWB对IEEE802.11a WLAN的电磁干扰分析

在FCC模板和ECC模板的基础上,分析了室内环境下UWB设备对IEEE802.11a WLAN系统的电磁干扰。在IEEE802.11a系统性能恶化1dB的情况下,使用双线模型分别计算出室内环境下单个UWB设备和多个UWB设备的发射功率限制。分析结果表明,对于IEEE802.11a WLAN来说,距离最近的UWB干扰是最主要的干扰,建议以36cm的最小隔离距离为基础来限制5GHz频段处的UWB发射功率。因此ECC模板更能满足IEEE802.11a的电磁兼容要求,而FCC模板能否保证有待进一步研究。     

一种用于数字电视接收机的58dB IRR CMOS镜像抑制混频器

The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters（PPF） are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio（IRR） of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm.     

A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of -15 dBm.     

MB-OFDM UWB通信空时网格编码误码率分析

 本文研究多带正交频分复用瑞利衰落信道中,空时网格编码发射天线间空间相关性的分集性能.空时网格编码将单个输出的编码符号转换成多个编码符号,并通过多个发射天线传输,在接收端,Viterbi优化软判决算法用于译码.我们分析了MB-OFDM系统在quasi-static和interleaved两种信道中相关空间衰落对误码率的影响.在空间相关性较小时,分集阶数能得到保持;而在空间相关性较大时,interleaved信道能保持分集阶数,quasi-static信道的分集阶数将减小.空时编码总体上对空间相关性表现出鲁棒性.     

一种高线性的UWB接收机下变频混频器设计

该文介绍了一种UWB下变频混频器的设计思路和技术。在TSMC0.18μmCMOS工艺下,使用Agilent公司的ADS软件设计出一种3~5GHz的CMOS混频器电路。仿真结果表明,工作电压3V时,RF频率为3.169GHz,本振频率为3.434GHz,中频频率为265MHz,转换增益为15.4dB,双边带噪声系数低于13.3dB,P1dB压缩点为-13dBm,工作电流为4.6mA。     

一种应用于双载波正交频分复用的超宽带单片射频收发机

本文给出了一种用于双载波正交频分复用的超宽带单片射频收发机芯片。该芯片采用直接变频结构,片内共集成了两路接收机,两路发射机,一个双载波频率综合器并提供控制收发机工作状态的三线串行接口。此芯片使用台积电 0.13 微米射频CMOS工艺制造,尺寸为 4.5mmx3.6mm。测试结果表明：该收发机的接收机链路噪声系数为 5~6.2dB,最大增益为 78~84dB,可变增益为 64dB,带内和带外三阶交调点分别为-6dBm和 4dBm,在所有频带上都获得良好的输入匹配（S11<-10）;该收发机的发射机最大可输出-5dBm 功率,带内主要杂散均小于 -33dBc（镜像抑制<-33dBc,载波泄露<-34dBc）,典型的输出三阶交调点为 6dBm;该收发机的双载波频率综合器可以同时输出两路频率可独立配置的载波信号,其跳频时间小于1.2ns。在1.2V单电源供电下,整个射频芯片消耗最大电流为420mA。     

改进的MB-OFDM UWB 信道估计算法

在MB-OFDM UWB 系统中,传统的信道估计方法没有充分利用信道长度这一信息,估计信道长度常大于实际长度,造成了性能损失。针对这一缺陷,提出一种新的信道估计算法。首先利用LS 算法估计出信道,然后通过信号能量估计(SEE)方法估计出信道长度。算法有效地降低了估计维数,因此提高了LS 算法的估计性能,同时对各算法的性能进行了分析比较。最后利用实验仿真证实了算法的有效性和分析的正确性。     

A 6-9 GHz 5-band CMOS synthesizer for MB-OFDM UWB

An ultra-wideband frequency synthesizer is designed to generate carrier frequencies for 5 bands distributed from 6 to 9 GHz with less than 3 ns switching time.It incorporates two phase-locked loops and one single-sideband (SSB) mixer.A 2-to-1 multiplexer with high linearity is proposed.A modified wideband SSB mixer,quadrature VCO, and layout techniques are also employed.The synthesizer is fabricated in a 0.18μm CMOS process and operates at 1.5-1.8 V while consuming 40 mA current.The measured phase noise ...