Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.     

Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.     

小偏压下阱中阱结构的量子隧穿特性及其实现

共振隧穿是电子的隧穿概率在某一个能量值附近以尖锐的峰值形式出现的隧穿,是目前为止最有希望应用到实际电路和系统的量子器件之一,其特点是器件的响应速度非常快。本文用传递矩阵的方法分别计算了在外加偏压下,对称双势垒、三势垒应变量子阱结构的透射系数与入射电子能量和隧穿电流与偏置电压的关系,模拟了应变多量子阱结构的隧穿系数和I-V特性曲线。计算得到隧穿电流峰值位置与实验测试值符合得很好,对于设计共振隧穿二极管并为进一步实验提供理论指导具有重要的意义。     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

利用FN振荡电流估计金属-氧化物-半导体场效应管Si-SiO_2界面宽度

利用聚合物材料研制出热光 Mach- Zehnder(MZ)型干涉调制器 ,单位相移为 1.5 3π/ (cm·℃ ) ,产生 π相移所需功率为 12 m W.热光开关的响应时间为 1.2 m s,消光比为 16 d B,接近实用水平 .并且讨论了热光相移在多种光电子器件中的应用     

Theoretical study of the SiO2/Si interface and its effect on energy band profile and MOSFET gate tunneling current

Two SiO_2/Si interface structures,which are described by the double bonded model(DBM) and the bridge oxygen model(BOM),have been theoretically studied via first-principle calculations.First-principle simulations demonstrate that the width of the transition region for the interface structure described by DBM is larger than that for the interface structure described by BOM.Such a difference will result in a difference in the gate leakage current. Tunneling current calculation demonstrates that the SiO_2/Si...     

Design space exploration of low-power flip-flops in FinFET technology

As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor sizing methods in FinFET technology to design the FF circuit based on different input and output capacitances. The results indicate that the circuit designed using minimum-energy-delay-area product (min-EDAP) approach has the lowest PDP. We developed a modified logical effort approach that leads to a minimum EDP design compared to the other approaches. The performance of flip-flop is also investigated based on the metrics extracted from energy efficient curve (EEC). Results show that the ED metric has the minimum EDP in all cases. Moreover, the E⁴D metric shows the least variations against frequency and voltage fluctuations, while the ED⁴ metric is more robust against temperature variations. Simulations are performed using HSPICE in 16 nm FinFET technology with shorted-gate (SG) mode configuration.     

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices

Double gate (DG) FETs have emerged as the most promising technology for sub-50 nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, viz., doped body symmetric device (SymDG) with polysilicon gates, intrinsic body symmetric device with metal gates (MGDG) and intrinsic body asymmetric device (AsymDG) with different front and back gate materials. It is observed that, use of (near-mid-gap) metal gate and intrinsic body can result in 3–4× reduction in gate-to-channel leakage compared to the SymDG structure.     

二氧化硅与硅界面及其对能带轮廓及MOSFET栅遂穿电流影响的理论研究

利用第一原理对双键及桥氧两种二氧化硅与硅界面模型进行了理论研究。结果表明双键模型的界面转变区宽度较大。这种差别会导致MOSFET栅漏电的不同。遂穿电流的计算表明界面双键模型结构有较大的栅漏电。     

基于25 nm FinFET结构的SRAM单粒子效应研究

对基于25 nm FinFET结构的SRAM单粒子效应进行研究。使用Synopsys Sentaurus TCAD仿真软件进行器件工艺校准,并对独立3D FinFET器件以及包含FinFET器件和HSpice模型的混合电路(如6管SRAM单元)进行单粒子瞬态仿真。通过改变重粒子入射条件,分析影响瞬态电流峰值、脉宽、漏极翻转阈值等参数的因素。研究发现,混合模型中,FinFET结构器件的漏极翻转阈值为0.023 MeV·cm²/mg,对未来基于FinFET结构的器件及电路结构的加固提出了更高的要求。     

Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices

In this work, we investigate the gate voltage and the geometry dependence of the series resistance and the carrier mobility in n-type and p-type FinFETs. A significant gate voltage dependence of the series resistance is observed, which is ascribed to the conduction modulation of the LDD region under the gate. The fin width dependence of the series resistance is investigated and two simple methods of normalization are compared. Mobility data in narrow (W_fin = 30 nm) and wide fin (W_fin = 3μm) have been compared. N-FinFETs show a higher mobility compared to the p-FinFET in both cases, but for narrow fins the difference is reduced since the mobility on the sidewalls improves for holes but degrades for electrons. We show that without taking into account the gate voltage dependence of the series resistance the mobility is significantly underestimated.     

Mobility analysis of surface roughness scattering in FinFET devices

This paper presents a mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. Using temperature dependent analysis of effective mobility, quantitative information about the influence of the roughness could be obtained directly on the device. The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. Using a conventional mobility model, it was possible to fit the gate voltage and temperature dependence of sidewall and top surface mobilities. This procedure allowed the contribution of the surface roughness scattering to be quantified with nondestructive characterization. Significant differences were observed for sidewalls and top surface. In the specific case under study, surface roughness scattering on sidewalls was about three times stronger than on top surface for n-channel FinFETs, whereas it remained similar for p-channel ones.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

纳米级MOSFET隧穿栅电流量子模型

运用一种全量子模型,研究高k栅介质纳米MOSFET(场效应管)栅电流,特别适用于各种材料高k栅介质和高k叠栅介质纳米MOSFET。使用该方法,研究了高k栅介质中氮含量等元素对栅极电流的影响,并对模拟结果进行了分析比较。结果显示,为了最大限度减少MOS器件的栅泄漏电流,需要优化介质中的氮含量。通过对比表明,模型与实验结果符合。     

14 nm FinFET工艺下栅隔离型二极管的ESD防护性能研究

当集成电路工艺进步到鳍式场效应晶体管(FinFET)技术节点时,二极管仍广泛用于输入/输出端口(I/O)的静电放电(ESD)防护工程,但二极管单位宽度鲁棒性比平面工艺有所降低。文章基于14 nm FinFET工艺,对栅隔离型二极管的失效电流(I_t2)、失效电压(V_t2)、单位宽度失效电流(I_t2/Width)以及单位面积失效电流(I_t2/Area)进行了详细研究,并给出了ESD器件特性随尺寸参数的变化趋势。实测数据表明,I_t2/Width随着Fin数目(n_fin)、沿Fin方向的倍乘因子(F_n)、垂直于Fin方向的倍乘因子(Y_array)等的增加均会有所降低,但I_t2/Area却有所提高,且开启电阻几乎不受n_fin和F_n的影响。     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

深亚微米MOS器件中栅介质层的直接隧穿电流

在WKB近似的理论框架下,提出了一个MOS器件中栅介质层直接隧穿电流的模型.在这个模型中,空穴量子化采用了一种改进的单带有效质量近似方法,这种方法考虑了价带的混合效应.通过与试验结果的对比,证明了这个模型可以适用于CMOS器件中电子和空穴的隧穿电流.还研究了介质层能隙中的色散对隧穿电流的影响.这个模型还可以进一步延伸到对未来高介电常数栅介质层中隧穿电流的研究.     

Analysis of flicker and thermal noise in p-channel Underlap DG FinFET

In this paper, we analyze the flicker and thermal noise model for underlap p-channel DG FinFET in weak inversion region. During the analysis of current and charge model, minimum channel potential i.e. virtual source is considered. Initially, the drain current for both long and short channel of DG FinFET are evaluated and found to be well interpreted with experimental results. Further, the flicker and thermal noise spectral density are derived. The flicker noise power spectral density is compared with published experimental results, which shows a good agreement between proposed model and experimental result. During calculation we have considered variation of scattering parameter and furthermore, the degradation of effective mobility is taken into account for ultrathin body. The variation of structural parameters such as gate length (L_g), body thickness (t_Si) and underlap length (L_un) are also considered. The degradation of gate noise voltage with frequency, underlap length and gate length signify that p-channel DG FinFET device can be a promising candidate for analog and RF applications.