Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

漂移区表面阶梯掺杂LDMOS的击穿电压模型

提出表面阶梯掺杂(SD：Step Doping on surface)LDMOS的二维击穿电压模型.基于求解多区二维Poisson方程,获得SD结构表面电场的解析式.借助此模型,研究其结构参数对击穿电压的影响;计算优化漂移区浓度和厚度与结构参数的关系,给出获得最大击穿电压的途径.数值结果,解析结果和试验结果符合较好.漂移区各区和衬底电场相互调制,在漂移区中部产生新的峰值,改善电场分布;高掺杂区位于表面,降低了正向导通电阻.结果表明：SD结构较常规结构击穿电压从192V提高到242V,导通电阻下降33%. 关键词： 阶梯掺杂 模型 优化 调制     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

Analysis of the modulation mechanisms of the electric field and breakdown performance in AlGaN/GaN HEMT with a T-shaped field-plate

A novel Al Ga N/Ga N high electron mobility transistor(HEMT) with a source-connected T-shaped field-plate(ST-FP HEMT) is proposed for the first time in this paper. The source-connected T-shaped field-plate(ST-FP) is composed of a source-connected field-plate(S-FP) and a trench metal. The physical intrinsic mechanisms of the ST-FP to improve the breakdown voltage and the FP efficiency and to modulate the distributions of channel electric field and potential are studied in detail by means of two-dimensional numerical simulations with Silvaco-ATLAS. A comparison to the HEMT and the HEMT with an S-FP(S-FP HEMT) shows that the ST-FP HEMT could achieve a broader and more uniform channel electric field distribution with the help of a trench metal, which could increase the breakdown voltage and the FP efficiency remarkably. In addition, the relationship between the structure of the ST-FP, the channel electric field, the breakdown voltage as well as the FP efficiency in ST-FP HEMT is analyzed. These results could open up a new effective method to fabricate high voltage power devices for the power electronic applications.     

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.     

Breakdown voltage analysis of Al0.25Ga0.75N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

In this paper,two-dimensional electron gas（2DEG） regions in AlGaN/GaN high electron mobility transistors（HEMTs） are realized by doping partial silicon into the AlGaN layer for the first time.A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge.The high electric field near the gate for the complete silicon doping structure is effectively decreased,which makes the surface electric field uniform.The high electric field peak near the drain results from the potential difference between the surface and the depletion regions.Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer.The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain.The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field.     

Breakdown voltage analysis of Al_0.25Ga_0.75N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

In this paper,two-dimensional electron gas(2DEG) regions in AlGaN/GaN high electron mobility transistors(HEMTs) are realized by doping partial silicon into the AlGaN layer for the first time.A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge.The high electric field near the gate for the complete silicon doping structure is effectively decreased,which makes the surface electric field uniform.The high electric field peak near the drain results from the potential difference between the surface and the depletion regions.Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer.The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain.The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field.     

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper for the first time, a partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) is proposed with a novel trench which improves breakdown voltage. The introduced trench in the partial buried oxide enhances peak of the electric field and is positioned in the drain side of the drift region to maximize breakdown voltage. We demonstrate that the electric field is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the trench-partial-silicon-on-insulator (T-PSOI) structure. Hence, a more uniform electric field is obtained. Two dimensional (2D) simulations show that the breakdown voltage of T-PSOI is nearly 64% higher in comparison with partial silicon on insulator (PSOI) structure and alleviate self heating effect approximately 9% and 15% in comparison with its conventional PSOI (C-PSOI) and conventional SOI (C-SOI) counterparts respectively. In addition the current of the T-PSOI, C-PSOI, conventional SOI (C-SOI), and fully depleted conventional SOI (FC-SOI) structures are 90, 82, 74, and 44 μA, respectively for a drain–source voltage V_DS = 30 V and gate–source voltage V_GS = 10 V.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

Effects of trench oxide and field plates on the breakdown voltage of SOI LDMOSFET

To improve the breakdown voltage, we propose a SOI-based LDMOSFET with a trench structure in the drift region. Due to the trench oxide and underneath boron implanted layer, the surface electric field in the drift region effectively reduced. These effects resulted in the increment of breakdown voltage for the trenched LDMOS more than 100 V compared with the conventional device. However, the specific on-resistance, which has a trade-off relationship, is slightly increased. In addition to the trench oxide on the device performance, we also investigated the influence of n− drift to n+ drain junction spacing on the off-state breakdown voltage. The measured breakdown voltages were varied more than 50 V with different n− to n+ design spaces and achieved a maximum value at L_DA = 2.0 μm. Moreover, the influence of field plate on the breakdown voltage of trench LDMOSFET was investigated. It is found that the optimum drain field plate over the field oxide is 8 μm.     

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_on,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R_on,sp compared to the SD device and HK device.     

A 4H-SiC merged P-I-N Schottky with floating back-to-back diode

A novel 4H-SiC merged P-I-N Schottky (MPS) with floating back-to-back diode (FBD), named FBD-MPS, is proposed and investigated by the Sentaurus technology computer-aided design (TCAD) and analytical model. The FBD features a trench oxide and floating P-shield, which is inserted between the P+/N-(PN) junction and Schottky junction to eliminate the shorted anode effect. The FBD is formed by the N-drift/P-shield/N-drift and it separates the PN and Schottky active region independently. The FBD reduces not only the V_turn to suppress the snapback effect but also the V_on at bipolar operation. The results show that the snapback can be completely eliminated, and the maximum electric field (E_max) is shifted from the Schottky junction to the FBD in the breakdown state.     

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

By solving the 2D Poisson's equation, analytical models are proposed to calculate the surface potential and electric field distributions of lateral power devices with arbitrary vertical doping profiles. The vertical and the lateral breakdown voltages are formulized to quantify the breakdown characteristic in completely-depleted and partially-depleted cases. A new reduced surface field (RESURF) criterion which can be used in various drift doping profiles is further derived for obtaining the optimal trade-off between the breakdown voltage and the on-resistance. Based on these models and the numerical simulation, the electric field modulation mechanism and the breakdown characteristics of lateral power devices are investigated in detail for the uniform, linear, Gaussian, and some discrete doping profiles along the vertical direction in the drift region. Then, the mentioned vertical doping profiles of these devices with the same geometric parameters are optimized, and the results show that the optimal breakdown voltages and the effective drift doping concentrations of these devices are identical, which are equal to those of the uniform-doped device, respectively. The analytical results of these proposed models are in good agreement with the numerical results and the previous experimental results, confirming the validity of the models presented here.     

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal-oxide semiconductor (LDMOS) with ultra-low specific onresistance (R on,sp ) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.     

Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS)

For the first time, the novel inserted P-layer in trench oxide of LDMOS structure (IPT-LDMOS) is proposed in which a trench oxide with inserted P-layer is considered in the drift region to improve the breakdown voltage. Our simulation with two dimensional ALTAS simulator shows that by determining the optimum doping concentration of the P-layer, the charges of the N-drift and P-layer regions would be balanced. Therefore, complete depletion at the breakdown voltage in the drift region happens. Also, electric field in the IPT-LDMOS is modified by producing additional peaks which decrease the common peaks near the drain and source junctions.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS (lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS (buffered SJ-LDMOS)结构基础上, 提出了一种具有N型缓冲层的REBULF (reduced BULk field) super junction LDMOS结构. 这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题, 使super junction的N区和P区电荷完全补偿, 而且同时利用REBULF的部分N型缓冲层电场调制效应, 在表面电场分布中引入新的电场峰而使横向表面电场分布均匀, 提高了器件的击穿电压. 通过优化部分N型埋层的位置和参数, 利用仿真软件ISE分析表明, 新型REBULF SJ-LDMOS 的击穿电压较一般LDMOS提高了49%左右, 较文献提出的buffered SJ-LDMOS结构提高了30%左右. 关键词： lateral double-diffused MOSFET super junction 击穿电压 表面电场     

阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.