Control of electric field in 4H-SiC UMOSFET: Physical investigation

In this paper, we show how breakdown voltage (V_BR) and the specific on-resistance (R_on) can be improved simply by controlling of the electric field in a power 4H-SiC UMOSFET. The key idea in this work is increasing the uniformity of the electric field profile by inserting a region with a graded doping density (GD region) in the drift region. The doping density of inserted region is decreased gradually from top to bottom, called Graded Doping Region UMOSFET (GDR-UMOSFET). The GD region results in a more uniform electric field profile in comparison with a conventional UMOSFET (C-UMOSFET) and a UMOSFET with an accumulation layer (AL-UMOSFET). This in turn improves breakdown voltage. Using two-dimensional two-carrier simulation, we demonstrate that the GDR-UMOSFET shows higher breakdown voltage and lower specific on-resistance. Our results show the maximum breakdown voltage of 1340 V is obtained for the GDR-UMOSFET with 10 µm drift region length, while at the same drift region length and approximated doping density, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 V and 703 V, respectively.     

Embedded-Ge source and drain in InGaAs/GaAs dual channel MESFET

We report the first demonstration of n-type III–V metal-semiconductor field-effect transistors (nMESFETs) with IV group material hetero-junction source and drain (S/D) technology. A selective epitaxial growth of germanium (Ge) in the recessed gallium arsenide (GaAs) S/D regions is successfully developed using ultra-high vacuum chemical vapor deposition (UHVCVD) system. The dual channel structure includes an additional 10-nm higher mobility n-In_0.2Ga_0.8As layer on n-GaAs channel and is introduced to further improve the device performance. The n-MESFET, combining embedded-Ge S/D with In_0.2Ga_0.8As/GaAs channel, exhibits good transfer properties with a drain current on/off ratio of approximately 10³. Due to the small barrier height of Ti/In_0.2Ga_0.8As Schottky contact, a lattice-matched wide bandgap In_0.49Ga_0.51P dielectric layer is also integrated into the device architecture to build a higher electron Schottky barrier height (SBH) for gate leakage current reduction. The Ti/In_0.49Ga_0.51P/n-In_0.2Ga_0.8As Schottky diode shows a comparable leakage level to Ti/n-GaAs with 2 × 10^?2 A/cm² at a gate voltage of ?2.0 V.     

New GaN Schottky barrier diode employing a trench on AlGaN/GaN heterostructure

A new GaN Schottky barrier diode employing a trench structure, which is proposed and fabricated, successfully decreases a forward voltage drop without sacrificing any other electric characteristics. The trench is located in the middle of Schottky contact during a mesa etch. The Schottky metal of Pt/Mo/Ti/Au is e-gun evaporated on the 300 nm-deep trench as well as the surface of the proposed GaN Schottky barrier diode. The trench forms the vertical Au Schottky contact and lateral Pt Schottky contact due to the evaporation sequence of Schottky metal. The forward voltage drops of the proposed diode and conventional one are 0.73 V and 1.25 V respectively because the metal work function (5.15 eV) of the vertical Au Schottky contact is considerably less than that of the lateral Pt Schottky contact (5.65 eV). The proposed diode exhibits the low on-resistance of 1.58 mΩ cm² while the conventional one exhibits 8.20 mΩ cm² due to the decrease of a forward voltage drop.     

Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.     

Device linearity improvement and current enhancement utilizing high-to-low doping-channel FETs

We report device linearity improvement and current enhancement in both a heterostructure FET (HFET) and a camel-gate FET (CAMFET) using InGaAs/GaAs high-low and GaAs high-medium-low doped channels, respectively. In an HFET, a low doped GaAs layer was employed to build an excellent Schottky contact. In a GaAs CAMFET, a low doped layer together withn⁺andp⁺layers formed a high-performance majority camel-diode gate. Both exhibit high effective potential barriers of >1.0 V and gate-to-drain breakdown voltages of >20.0 V (atI_g=1.0 mA mm⁻¹). A thin, high doped channel was used to enhance current drivability and to improve the transconductance linearity. A 2×100 μm²HFET had a peak transconductance of 230 mS mm⁻¹and a current density greater than 800 mA mm⁻¹. The device had a transconductance of more than 80 percent of the peak value over a wide drain current range of 200 to 800 mA mm⁻¹. A 1.5×100 μm²CAMFET had a peak transconductance of 220 mS mm⁻¹and a current density greater than 800 mA mm⁻¹. Similarly, the device had a transconductance of more than 80 percent of the peak value over a wide drain current range of 160 to 800 mA mm⁻¹. The improvement of device linearity and the enhancement of current density suggest that high-to-low doped-channel devices for both an HFET and a CAMFET are suitable for high-power large signal circuit applications.     

A novel power UMOSFET with a variable K dielectric layer

A novel split-gate power UMOSFET with a variable K dielectric layer is proposed.This device shows a 36.2% reduction in the specific on-state resistance at a breakdown voltage of 115 V,as compared with the SGE-UMOS device.Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV2/RON,as compared with the previous power UMOSFET.     

Characterization of a a-Si:H thin-film transistors and the effect of thermal annealing

An analysis of characteristics of a-Si:H thin-film transistors were performed. The mobility of electrons in the accumulation layer induced by a gate voltage was in a order of 0.5 cm²/V · s at a field strength lower than 1×10⁴V/cm, and proportional toE ^–r at higher electric field, wherer was 0–0.2.The effect of thermal annealing at the temperatures 100–160°C on the parametersV _T andr are discussed. The activation energies for the variation of both parameters were 0.31 eV and 0.33 eV, respectively, that suggests the mechanism influencing both parameters may be the same. The mechanism is discussed in relation to the carrier hopping through the network of localized states.     

In–Ga–Zn–O MESFET with transparent amorphous Ru–Si–O Schottky barrier

Rectifying transparent amorphous Ru–Si–O Schottky contacts to In–Ga–Zn–O have been fabricated by means of reactive sputtering without any annealing processes nor semiconductor surface treatments. The ideality factor, effective Schottky barrier height and rectification ratio are equal to 1.6, 0.9 eV and 10⁵ A/A, respectively. Ru–Si–O/In–Ga–Zn–O Schottky barriers were employed as gate electrodes for In–Ga–Zn–O metal–semiconductor field‐effect transistors (MESFETs). MESFET devices exhibiting on‐to‐off current ratio at the level of 10³ A/A in a voltage range of 2 V, with subthreshold swing equal to 420 mV/dec were demonstrated. A channel mobility of 7.36 cm²/V s was achieved. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Enhanced electrical properties of pentacene-based organic thin-film transistors by modifying the gate insulator surface

A reliable surface treatment for the pentacene/gate dielectric interface was developed to enhance the electrical transport properties of organic thin-film transistors (OTFTs). Plasma-polymerized fluorocarbon (CFx) film was deposited onto the SiO₂ gate dielectric prior to pentacene deposition, resulting in a dramatic increase of the field-effect mobility from 0.015 cm²/(V s) to 0.22 cm²/(V s), and a threshold voltage reduction from −14.0 V to −9.9 V. The observed carrier mobility increase by a factor of 10 in the resulting OTFTs is associated with various growth behaviors of polycrystalline pentacene thin films on different substrates, where a pronounced morphological change occurs in the first few molecular layers but the similar morphologies in the upper layers. The accompanying threshold voltage variation suggests that hole accumulation in the conduction channel-induced weak charge transfer between pentacene and CFx.     

Junction barrier Schottky rectifier with an improved P-well region

<正>A junction barrier Schottky（JBS） rectifier with an improved P-well on 4H-SiC is proposed to improve the V_F-I_R trade-off and the breakdown voltage.The reverse current density of the proposed JBS rectifier at 300 K and 800 V is about 3.3×10^-8 times that of the common JBS rectifier at no expense of the forward voltage drop.This is because the depletion layer thickness in the P-well region at the same reverse voltage is larger than in the P⁺ grid,resulting in a lower spreading current and tunneling current.As a result,the breakdown voltage of the proposed JBS rectifier is over 1.6 kV,that is about 0.8 times more than that of the common JBS rectifier due to the uniform electric field.Although the series resistance of the proposed JBS rectifier is a little larger than that of the common JBS rectifier,the figure of merit（FOM） of the proposed JBS rectifier is about 2.9 times that of the common JBS rectifier.Based on simulating the values of susceptibility of the two JBS rectifiers to electrostatic discharge（ESD） in the human body model（HBM） circuits,the failure energy of the proposed JBS rectifier increases 17%compared with that of the common JBS rectifier.     

Improved electrical and interfacial properties of RF-sputtered HfAlOx on n-GaAs with effective Si passivation

In this paper, we present the effects of ultrathin Si interfacial layer on the physical and electrical properties of GaAs MOS capacitors fabricated using RF-sputtered HfAlO_x gate dielectric. It is found that HfAlO_x/Si/n-GaAs stack exhibits excellent electrical properties with low frequency dispersion (∼4.8%), hysteresis voltage (0.27 V) and interface trap density (1.3 × 10¹² eV⁻¹ cm⁻²). The current density of 3.7 × 10⁻⁵ A/cm² is achieved with an equivalent-oxide-thickness of 1.8 nm at V_FB + 1 V for Si-passivated HfAlO_x films on n-GaAs. X-ray photoelectron spectroscopy (XPS) analysis shows that the suppression of low-k interfacial layer formation is accomplished with the introduction of ultrathin Si interface control layer (ICL). Thus the introduction of thin layer of Si between HfAlO_x dielectrics and GaAs substrate is an effective way to improve the interface quality such as low frequency dispersion, hysteresis voltage and leakage current. Additionally, current conduction mechanism has been studied and the dominant conduction mechanisms are found to be Schottky emission at low to medium electric fields and Poole-Frenkel at high fields and high temperatures under substrate injection. In case of gate injection, the main current conduction at low field is found to be the Schottky emission at high temperatures.     

Millimeter-wave Detectors Based on Antenna-coupled Low-barrier Schottky Diodes

The principles of construction of millimeter wave detectors based on low-barrier Schottky diodes and planar antennas are discussed. The modified planar slot antenna with low beam spillover at the resonant frequency of 94 GHz has been developed. Experiments have been carried out to investigate detecting characteristics of the diodes with differential contact resistances at zero bias. Experimental data are well correspond to calculations in a simple model of detector. At the maximum of rf-to-dc voltage sensitivity - more than 10000 V/W - is obtained. At lower values of a better noise equivalent power (NEP), around 10⁻¹² W Hz^−1/2, is predicted.     

Electrical characteristics of Ta2O5 based capacitors with different gate electrodes

Al, W and TiN gate stacks using reactively sputtered thin (15–35 nm) Ta₂O₅ as a high-k dielectric have been investigated. It has been established that the type and the deposition technique of the gate electrode strongly affect the parameters of the structures. RF sputtered tungsten has been established as the most suitable electrode material (giving a nonreactive contact) providing a low leakage current (∼10^-8 A/cm² at 1 MV/cm) through capacitors and a high dielectric constant. The application of Al gate electrodes in the advanced DRAM devices is impeded by the chemical interaction of Al with the Ta₂O₅ films deteriorating the performance of the structures. The radiation-induced defects during the TiN deposition increase the leakage currents for TiN/Ta₂O₅/Si capacitors. A modified Poole–Frenkel conduction mechanism with a tendency for a reduction of the compensation level with increasing Ta₂O₅ thickness was found for W-gate capacitors. Schottky emission at low applied fields and modified Poole–Frenkel mechanism at high fields define the J–V characteristics of Al capacitors. The current through TiN capacitors is governed by ohmic and space charge limited conduction. The post metallization annealing in H₂ reduces the oxide charge but deteriorates both the breakdown fields and the leakage currents for all capacitors studied. The effect is stronger for Al and TiN structures and is accompanied by a reduction of the dielectric constant. PACS 72.80.Sk; 73.40.Qv; 77.55+f; 81.15 Cd     

High-Power GaN Electronic Devices

Gallium Nitride (GaN) and related materials (especially AlGaN) recently have attracted a lot of interest for applications in high-power electronics capable of operation at elevated temperatures and high frequencies. The AlGaInN system offers numerous advantages. These include wide bandgaps, good transport properties, the availability of heterostructures (particularly AlGaN/GaN), the experience base gained by the commercialization of GaN-based laser and light-emitting diodes and the existence of a high growth rate epitaxial method (hydride vapor phase epitaxy, HVPE) for producing very thick layers or even quasisubstrates. These attributes have led to rapid progress in the realization of a broad range of GaN electronic devices. Al_xGa_1-xN (x=0 ～.25) Schottky rectifiers were fabricated in a lateral geometry employing p⁺-implanted guard rings and rectifying contact overlap onto an SiO₂ passivation layer. The reverse breakdown voltage (V_B) increased with the spacing between Schottky and ohmic metal contacts, reaching 9700 V for Al_0.25Ga_0.75N and 6350 V for GaN, respectively, for 100-µm gap spacing. Assuming lateral depletion, these values correspond to breakdown field strengths of <9.67×10⁵ Vcm^?2, which is roughly a factor of 5 lower than the theoretical maximum in bulk GaN. The figure of merit (V_B)²/R_ON, where RON is the on-state resistance, was in the range 94 to 268 MWcm^?2 for all the devices. Edge-terminated Schottky rectifiers were also fabricated on quasibulk GaN substrates grown by HVPE. For small-diameter (75?µm) Schottky contacts, Vs measured in the vertical geometry was ～700?V, with an on-state resistance (RON) of 3?mΩcm², producing a figure-of-merit V_B ²/R_ON of 162.8?MW-cm^?2. GaN p-i-n diodes were also fabricated. A direct comparison of GaN p-i-n and Schottky rectifiers fabricated on the same GaN wafer showed higher reverse breakdown voltage for the former (490?V vs. 347?V for the Schottky diodes), but lower forward turn-on voltages for the latter (～3.5?V vs. ～5?V for the p-i-n diodes). The forward I-V characteristics of the p-i-n rectifiers show behavior consistent with a multiple recombination center model. The reverse current in both types of rectifiers was dominated by surface perimeter leakage at moderate bias. Finally, all of the devices we fabricated showed negative temperature coefficients for reverse breakdown voltage, which is a clear disadvantage for elevated temperature operation. Bipolar devices are particularly interesting for high current applications such as microwave power amplifiers for radar, satellite, and communication in the l～5?GHz range, powers >l00?W, and operating temperatures >425°C. pnp Bipolar Junction Transistors and pnp Heterojunction Bipolar Transistors were demonstrated for the first time. For power microwave applications, small area self-aligned npn GaN/AlGaN HBTs were attempted. The devices showed very promising direct current characteristics.     

Electric field breakdown of lateral-type Schottky diodes formed on lightly doped homoepitaxial diamond

The reverse current of lateral-type Schottky diodes fabricated on p-type homoepitaxial diamond was analyzed by changing the distance between Schottky and Ohmic electrodes and the metal materials in the Schottky electrodes. The maximum electric field at breakdown was 0.56 MV cm⁻¹ for the Au Schottky contact and less than 0.26 MV cm⁻¹ for the Al Schottky contact. The breakdown voltage depended on the electrode distance when the diamond surface was revealed in vacuum, whereas the Schottky diodes sustained the applied voltage of 500 V, corresponding to 0.69 MV cm⁻¹, after covering of the diamond surface with an insulating liquid. Diamond surface protection is an indispensable technique for fabrication of high-voltage Schottky diodes based on diamond.     

Electrical behaviour of lateral Al/n-GaN/Al structures

The electrical behaviour of lateral Al/n-GaN/Al structures has been studied by current-voltage measurements between a large pad with an area of 22 mm² and small contacts with different areas in the range of 0.01-1 mm². The results indicated that near room temperature the current was limited by the GaN layer exhibiting linear I-V characteristics for large contacts around 1 mm², while it was contact limited for small contacts around 0.1 mm² and below. This indicates that the same metal contact can behave as ohmic or rectifying depending on the contact area and so on the ratio of contact resistance to the series resistance of the structure.Near liquid nitrogen temperature, the current through the lateral Al/n-GaN/Al structures was limited by space charges. The Al/n-GaN contacts exhibited a very low Schottky barrier height below or around 0.2 eV. A new possible mechanism responsible for the temperature dependence of the ideality factor is proposed.     

Optimization of the UV CuII laser

The cw output power of the uv CuII laser has been optimized with respect to the hollow cathode geometry, the discharge current, the fill gas pressure and the resonator mirror parameters. A maximum laser output power of 900 mW for multiline operation at 248.6, 259.1, 260.0, and 270.3 nm was achieved with 100 A discharge current, 260 V voltage and 16 mbar fillgas pressure, when a hollow cathode of 1.2 m length and 2×6 mm² cross section was employed. The single-pass pain gl has been estimated to 7%. A hollow cathode cross section of 1.5×4.5 mm² is suggested as an optimum geometry. In addition, some investigations on the mechanism of the laser power decay in Ne–Cu-discharges are presented.     

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m ^{− 1}on-current and on/off current ratios of 10⁶, for a conservative oxide thickness of 40 Å and | V_g − V_t| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | V_t| is obtained in devices with gate lengths ranging from 100 to 20 nm.     

A p-channel SMC poly-Si thin film-transistor with a GOLDD structure

We have developed a silicide-mediated crystallization (SMC) polycrystalline silicon (poly-Si) thin film transistor (TFT) with a gate overlapped lightly doped drain (GOLDD) structure. Applying a GOLDD structure to the SMC poly-Si TFT, the off-state leakage current of coplanar TFT is reduced, while the reduction of the on-state current is relatively small. The p-channel poly-Si TFT with a GOLDD structure exhibited a field effect mobility of 50 cm²/V s and an off-state leakage current of 3.8×10⁻¹¹ A/μm at the drain voltage of −5 V and the gate voltage of 10 V.     

W掺杂ZnO透明导电薄膜的理论及实验研究

本文从理论与实验两方面入手, 对高价态差金属W掺杂ZnO (WZO) 薄膜材料的特性进行分析讨论. 采用基于密度泛函理论的平面波赝势方法对WZO材料特性进行理论分析, 计算结果表明: W以替位形式掺入ZnO六角纤锌矿晶格结构中, 由于W-O键的键长较长引起晶格常数增加, 产生晶格畸变; 掺杂后费米能级进入导带, 其附近的导电电子主要由W 5d, O 2p及Zn 3d电子轨道提供, 材料表现出n型半导体的特性; 同时能带简并效应使其光学带隙展宽. 为进一步验证该理论分析结果的适用性, 本文采用脉冲直流磁控溅射技术进行了本征ZnO及WZO薄膜的实验研究, 结果表明: W掺入未改变ZnO的生长方式, 但引起薄膜的晶格常数增加, 电阻率由本征ZnO的1.35× 10^-2 Ω·cm减小到1.55× 10^-3 Ω·cm, 光学带隙由3.27 eV展宽到3.48 eV. 制备的WZO薄膜在400-1100 nm的平均透过率大于83%. 实验结果对理论计算结果进行了验证, 表明WZO薄膜作为透明导电薄膜的应用潜力.