Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson’s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal–oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-kappa gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-kappa gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-kappa dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride (HfSiON) on ultrathin SiO₂ buffer layer. The gate dielectric with 10? (1?= 0.1 nm) equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant (k=14) and low gate-leakage current (I_g=1.9×10^-3A/cm² @V_g=V_fb-1V for EOT of 10?). TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.     

单轴应变硅N沟道金属氧化物半导体场效应晶体管电容特性模型

电容特性模型是单轴应变硅金属氧化物半导体场效应晶体管(Si MOSFET)和电路进行瞬态分析、交流小信号分析、噪声分析等的重要基础. 本文首先建立了单轴应变Si NMOSFET 的16 个微分电容模型, 并将微分电容的仿真结果与实验结果进行了比较, 验证了所建模型的正确性. 同时对其中的关键性栅电容C_gg 与应力强度、偏置电压、沟道长度、栅极掺杂浓度等的关系进行了分析研究. 结果表明, 与体硅器件相比, 应变的引入使得单轴应变Si NMOSFET器件的栅电容增大, 随偏置电压、沟道长度、栅极掺杂浓度的变化趋势保持不变.     

AlGaN/GaN高电子迁移率器件外部边缘电容的物理模型

AlGaN/GaN HEMT外部边缘电容Cofd是由栅极垂直侧壁与二维电子气水平壁之间的电场构成的等效电容.本文基于保角映射法对Cofd进行物理建模,考虑沟道长度调制效应,研究外部偏置、阈值电压漂移和温度变化对Cofd的影响:随着漏源偏压从零开始增加,Cofd先保持不变再开始衰减,其衰减速率随栅源偏压的增加而减缓;AlGaN势垒层中施主杂质浓度的减小和Al组分的减小都可引起阈值电压的正向漂移,正向阈值漂移会加强沟道长度调制效应对Cofd的影响,导致Cofd呈线性衰减.在大漏极偏压工作情况下,Cofd对器件工作温度的变化更加敏感.     

超短沟道绝缘层上硅平面场效应晶体管中热载流子注入应力导致的退化对沟道长度的依赖性

随着场效应晶体管(MOSFET)器件尺寸的进一步缩小和器件新结构的引入, 学术界和工业界对器件中热载流子注入(hot carrier injections, HCI)所引起的可靠性问题日益关注. 本文研究了超短沟道长度(L=30–150 nm)绝缘层上硅(silicon on insulator, SOI)场效应晶体管在HCI应力下的电学性能退化机理. 研究结果表明, 在超短沟道情况下, HCI 应力导致的退化随着沟道长度变小而减轻. 通过研究不同栅长器件的恢复特性可以看出, 该现象是由于随着沟道长度的减小, HCI应力下偏压温度不稳定性效应所占比例变大而导致的. 此外, 本文关于SOI器件中HCI应力导致的退化和器件栅长关系的结果与最近报道的鳍式场效晶体管(FinFET)中的结果相反. 因此, 在超短沟道情况下, SOI平面MOSFET器件有可能具有比FinFET器件更好的HCI可靠性.     

Gate control characteristics in GaAs nanometer-scale Schottky wrap gate structures

Gate control characteristics of GaAs-based quantum wire transistors (QWRTrs) controlled by a nanometer-scale Schottky wrap gate (WPG) are investigated theoretically and experimentally. Gate bias dependence of the effective wire width of fabricated WPG QWRTrs determined theoretically as well as experimentally from Landau plots showed that the nanometer-scale WPG controls the potential very tightly near channel pinch-off and that the pinch-off threshold voltage is strongly dependent on the gate length, L_G, when L_G is shorter than 400 nm. The theory based on the three-dimensional (3D) potential simulation pointed out that Fermi level pinning on the semiconductor surface around the WPGs strongly affects the gate controllability in the nanometer-scale Schottky WPG structure.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

Ge组分对应变Si1-xGe x 沟道p-MOSFET电学特性影响

利用二维数值模拟方法,研究了不同Ge组分应变Si_1-xGe _x 沟道p-MOSFET的电容-电压特性以及阈值电压的变化情况.计算结果表明:提高应变Si_1-xGe _x 沟道层中的Ge组分,器件亚阈值电流明显增大;栅电容在器件进入反型状态时产生显著变化;阈值电压的改变量与Ge组分基本成线性关系.通过改变Si_1-xGe _x 沟道的长度,并结 关键词： 1-xGe _x 沟道')" href="#">应变Si_1-xGe _x 沟道 p-MOSFET 空穴迁移率 栅电容     

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μ m thick thin-layer SOI.     

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two- dimensional Poisson’s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor (SMGFET).     

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal-oxide semiconductor (LDMOS) with ultra-low specific onresistance (R on,sp ) is proposed. The structure features a dual gate (DG LDMOS): a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage (BV). Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.     

Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process

A double-recessed offset gate process technology for InP-based high electron mobility transistors (HEMTs) has been developed in this paper. Single-recessed and double-recessed HEMTs with different gate offsets have been fabricated and characterized. Compared with single-recessed devices, the maximum drain-source current (I_D,max) and maximum extrinsic transconductance (g_m,max) of double-recessed devices decreased due to the increase in series resistances. However, in terms of RF performance, double-recessed HEMTs achieved higher maximum oscillation frequency (f_MAX) by reducing drain output conductance (g_ds) and drain to gate capacitance (C_gd). In addition, further improvement of f_MAX was observed by adjusting the gate offset of double-recessed devices. This can be explained by suppressing the ratio of C_gd to source to gate capacitance (C_gs) by extending drain-side recess length (L_rd). Compared with the single-recessed HEMTs, the f_MAX of double-recessed offset gate HEMTs was increased by about 20%.     

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs

The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio frequency(RF)performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage(Vth) of 60 m V than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length,which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the In Ga As channel so that the transconductance(gm) of the high gate stem device is 70 m S/mm larger than that of the short stem device. As for the RF performances,the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum ft of 270 GHz and fmax of 460 GHz, while the short gate stem device has a maximum ft of 240 GHz and the fmax of 370 GHz.     

Annealing Characteristics of ultra—thin high—K HfO2 gate dielectrics

Ultra-thin HfO2 gate-dielectric films were fabricated by ion-beam sputtering a sintered HfO2 target and subsequently annealed at different temperatures and atmospheres.We have studied the capacitance-voltage,current-voltage,and breakdon characteristics of the gate dielectrics.The results show that electrical characteristics of HfO2 gate dielectric are related to the annealing temperature.With increase annealing temperature,the largest value of capacitance decreases,the equivalent oxide thickness increases,the leakage current reduces,and the breakdown voltage decreases.     

Equivalent oxide thickness scaling of Al2O3/Ge metal-oxide-semiconductor capacitors with ozone post oxidation

Aluminum-oxide films deposited as gate dielectrics on germanium （Ge） by atomic layer deposition were post oxidized in an ozone atmosphere. No additional interfacial layer was electron microscopy and X-ray photoelectron spectroscopy detected by the high-resolution cross-sectional transmission measurements made after the ozone post oxidation （OPO） treatment. Decreases in the equivalent oxide thickness of the OPO-treated Al2O3/Ge MOS capacitors were confirmed. Furthermore, a continuous decrease in the gate leakage current was achieved with increasing OPO treatment time. The results can be attributed to the film quality having been improved by the OPO treatment.     

异质栅全耗尽应变硅金属氧化物半导体模型化研究

为了进一步提高小尺寸金属氧化物半导体(MOSFET)的性能,在应变硅器件的基础上, 提出了一种新型的异质栅MOSFET器件结构.通过求解二维Poisson方程,结合应变硅技术的物理原理,建立了表面势、表面电场以及阈值电压的物理模型,研究了栅金属长度、功函数以及双轴应变对其的影响. 通过仿真软件ISE TCAD进行模拟仿真,模型计算与数值模拟的结果基本符合. 研究表明：与传统器件相比,本文提出的异质栅应变硅新器件结构的载流子输运效率进一步提高, 可以很好地抑制小尺寸器件的短沟道效应、漏极感应势垒降低效应和热载流子效应, 使器件性能得到了很大的提升. 关键词： 应变硅 异质栅 阈值电压 解析模型     

Improvement of breakdown characteristics of an A1GaN/GaN HEMT with a U-type gate foot for millimeter-wave power application

<正>In this study,the physics-based device simulation tool Silvaco ATLAS is used to characterize the electrical properties of an AlGaN/GaN high electron mobility transistor(HEMT) with a U-type gate foot.The U-gate AlGaN/GaN HEMT mainly features a gradually changed sidewall angle,which effectively mitigates the electric field in the channel, thus obtaining enhanced off-state breakdown characteristics.At the same time,only a small additional gate capacitance and decreased gate resistance ensure excellent RF characteristics for the U-gate device.U-gate AlGaN/GaN HEMTs are feasible through adjusting the etching conditions of an inductively coupled plasma system,without introducing any extra process steps.The simulation results are confirmed by experimental measurements.These features indicate that U-gate AlGaN/GaN HEMTs might be promising candidates for use in miltimeter-wave power applications.