A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂ /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson’s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson’s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

Flat-band voltage shift in metal-gate/high-k/Si stacks

In metal-gate/high-k stacks adopted by the 45 nm technology node, the flat-band voltage (V_fb) shift remains one of the most critical challenges, particularly the flat-band voltage roll-off (V_fb roll-off) phenomenon in p-channel metal-oxide-semiconductor (pMOS) devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the V_fb shift and the origin of the V_fb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the V_fb shift phenomenon are summarized and the future research trend is described.     

稀土元素掺杂的Hf基栅介质材料研究进展

随着金属氧化物半导体场效应管(MOSFETs)等比缩小到45 nm技术节点,具有高介电常数的栅介质材料(高k材料)取代传统的SiO₂已经成为必然,然而Hf基高k材料在实际应用中仍然存在许多不足,而稀土元素掺杂在提高Hf基栅介质材料的k值、降低缺陷密度、调整MOSFETs器件的阈值电压等方面表现出明显的优势.本文综述了Hf基高k材料的发展历程,面临的挑战,稀土掺杂对Hf基高k材料性能的调节以及未来研究的趋势. 关键词： k栅介质')" href="#">Hf基高k栅介质 稀土掺杂 氧空位缺陷 有效功函数     

高k栅介质应变Si SOI MOSFET的阈值电压解析模型

在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOI MOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介 关键词： 应变Si k栅')" href="#">高k栅 短沟道效应 漏致势垒降低     

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al₂O₃/LaTiON-LaON/SiO₂/Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO₂ (2.3 eV).     

Soft X-ray photoemission study of nitrogen diffusion in TiN/HfO:N gate stacks

The impact of HfO:N post nitridation anneal (PNA) and gate fabrication on the physico-chemical properties of the TiN/HfO:N/SiO₂/Si stack are investigated using Soft X-ray Photoelectron Spectroscopy (S-XPS) and Vacuum UltraViolet Spectroscopic Ellipsometry (VUV-SE). Defects created in the high-k during plasma nitridation are passivated by PNA under O₂. Both oxygen and nitrogen diffusion is observed towards the bottom SiO₂/Si interface together with a regrowth of the SiO₂. These defects play a major role regarding nitrogen diffusion during gate fabrication. Without PNA, no diffusion is observed because O and N atoms are trapped inside the high-k. With PNA and simultaneous defects passivation, nitrogen from both metal gate and high-k diffuses towards the bottom SiO₂/Si interface.     

高k介质在新型半导体器件中的应用

当CMOS器件特征尺寸缩小到45 nm以下, SiO₂作为栅介质材料已经无法满足性能和功耗的需要, 用高 k材料替代SiO₂是必然选择. 然而, 由于高 k材料自身存在局限性, 且与器件其他部分的兼容性差, 产生了很多新的问题如界面特性差、 阈值电压增大、 迁移率降低等. 本文简要回顾了高 k栅介质在平面型硅基器件中应用存在的问题以及从材料、 结构和工艺等方面采取的解决措施, 重点介绍了高k材料在新型半导体器件中的应用, 并展望了未来的发展趋势.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Engineering of tunnel barrier for highly integrated nonvolatile memory applications

In this paper, the engineered tunnel barrier technology is introduced by using the engineered tunnel barrier of VARIOT type (SiO₂/Si₃N₄/SiO₂) and CRESTED type (Si₃N₄/SiO₂/Si₃N₄) with Si₃N₄ and high-k HfO₂ layers as charge trapping layers, respectively. In addition, the high-k stacked VARIOT type of SiO₂/HfO₂/Al₂O₃ and Al₂O₃/HfO₂/Al₂O₃ are compared with O/N/O tunnel barrier memory. As a result, the engineered tunnel barrier memory device showed excellent memory characteristics compared to the single SiO₂ tunnel barrier memory device, such as very high P/E (program/erase) speed, good retention time and no degradation in endurance characteristics.     

Ta2Si short time thermal oxidized layers in N2O and O2 to form high-k gate dielectric on SiC

In this work, we report on two properties of the oxidation of tantalum silicide (Ta₂Si) on SiC substrates making this material of interest as insulator for many wide bandgap or compound semiconductors. The relatively high oxidation rate of tantalum silicide to form high-k insulator layers and its ability for being oxidized in diluted N₂O ambient in a manner similar to the oxidation in O₂ are investigated. Metal-insulator-semiconductor capacitors have been used to establish the actual applicability and constrain of the high-k insulator depending on the oxidation conditions. At 1050 °C, the reduction of the oxidation time from 1 h to 5 min affects primordially the SiO_x interfacial layer formed between the bulk insulator and the substrate. This interfacial layer strongly influences the metal-insulator-semiconductor performances of the oxidized Ta₂Si layer. The bulk insulator basically remains unaffected although some structural differences arise when the oxidation is performed in N₂O.     

高k介质异质栅全耗尽SOI MOSFET二维解析模型

为了研究高介电常数(高k)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合. 关键词： 异质栅 绝缘衬底上的硅 阈值电压 解析模型     

Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO₂/HfSiO/SiO₂ trilayer and HfTiSiO/SiO₂ bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO₂ underlayers degrades the EOT-J_g characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO₂ capping for improving EOT-J_g characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10⁻² A/cm² for a TiO₂/HfSiO/SiO₂ trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.     

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO₂ layer and are then fully covered by a HfO₂ layer. The HfO₂ is a high-k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance–voltage and conductance–voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.     

p型硅MOS结构Si/SiO2界面及其附近的深能级与界面态

用深能级瞬态谱(DLTS)技术系统研究了Si/SiO₂界面附近的深能级和界面态。结果表明,在热氧化形成的Si/SiO₂界面及其附近经常存在一个浓度很高的深能级,它具有若干有趣的特殊性质,例如它的DLTS峰高度强烈地依赖于温度,以及当栅偏压使费密能级与界面处硅价带顶的距离明显小于深能级与价带顶的距离时,仍然可以观测到一个很强的DLTS峰。另外,用最新方法测量的Si/SiO₂界面连续态的空穴俘获截面与温度有关,而与能量位置无明显关系,DLTS测 关键词：     

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench(HK TG VDMOS) is proposed in this paper.The HK TG VDMOS features a high-k(HK) trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage(BV).Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction(SJ) vertical double-diffused metal-oxide semiconductor(VDMOS),the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS(TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Stability and band offsets between Si and LaAlO<Subscript>3</Subscript>

The replacement of traditional SiO₂ with high-k oxides allows the physical thickness of the gate dielectric to be thinner without the tunneling problem in Si-based metal-oxide-semiconductor field-effect transistors. LaAlO₃ appears to be a promising high-k material for use in future ultra large scale integrated devices. In the present paper, the electronic properties of Si/LaAlO₃ (001) heterojunctions are investigated by first-principles calculations. We studied the initial adsorption of Si atoms on the LaAlO₃ (001) surface, and found that Si atoms preferentially adsorb on top of oxygen atoms at higher coverage. The surface phase diagrams indicate that Si atoms may substitute oxygen atoms at the LaO-terminated surface. The band offsets, electronic density of states, and atomic charges are analyzed for the various Si/LaAlO₃ heterojunctions. Our results suggest that the Si/AlO₂ interface is suitable for the design of metal oxide semiconductor devices because the valence and conduction band offsets are both larger than 1 eV.     

Improved characteristics for MOHOS memory with oxygen-rich GdO as charge storage layer annealed by NH3

Characteristics of metal–oxide–high-k–oxide–silicon (MOHOS) memories with oxygen-rich or oxygen-deficient GdO as charge storage layer annealed by NH₃ or N₂ are investigated. Transmission electron microscopy, X-ray photoelectron spectroscopy and X-ray diffraction are used to analyze the cross-sectional quality, composition and crystallinity, respectively, of the stacked gate dielectric with a structure of Al/Al₂O₃/GdO/SiO₂/Si. The MOHOS capacitor with oxygen-rich GdO annealed in NH₃ exhibits a good trade-off among its memory properties: large memory window (4.8 V at ±12 V, 1 s), high programming speed (2.6 V at ±12 V/100 μs), good endurance and retention properties (window degradation of 5 % after 10⁵ program/erase cycles and charge loss of 18.6 % at 85 °C after 10 years, respectively) due to passivation of oxygen vacancies, generation of deep-level traps in the grain boundaries of the GdO layer and suppression of the interlayer between GdO and SiO₂ by the NH₃ annealing.