A satisfiability formulation for FPGA routing with pin rearrangements

This paper presents a satisfiability formulation for FPGA segmented channel routing with pin rearrangements. In our new routing model, the pins in each module have certain degree of freedom to be rearranged. With this flexibility, the wire routability can be improved in segmented channel routing. We present an efficient SAT-based approach to solve the problem. We use one of the best SAT-solvers, zChaff, to perform our experiments. Experimental results show the promising performance of the method.     

Novel Test Approach for Interconnect Resources in Field Programmable Gate Arrays

A novel test approach for interconnect resources(IRs)in field programmable gate arrays (FPGA)has been proposed.In the test approach,SBs (switch boxes)of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks(CLBs)in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip(SoC)hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.     

Simple method of asynchronous circuits implementation in commercial FPGAs

This paper presents a simple implementation method of pipelined asynchronous circuits, suitable for commercial field programmable gate arrays (FPGAs). Contrary to other existing asynchronous design techniques, the presented method does not require the application of additional user actions such as constraining or building hard macros. As a design example, an architecture of the asynchronous PicoBlaze compatible microcontroller and 12-bit pipelined fast array multiplier have been considered. The developed synchronous and asynchronous versions of the microcontroller as well as fast array multiplier have been implemented and tested using Xilinx FPGAs, and then compared in terms of the area requirement, power consumption and performance.     

低旁瓣球面共形随机稀疏阵列

针对平面阵列不能实现大范围空域扫描,角度分辨率不高的缺点,对比分析了球面共形阵列的辐射优点,后采用均匀随机排列的方法对球面共形阵列进行稀疏,最终在高角度分辨率和较低成本间实现了很好的性价比折衷,有很大实际意义。     

Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit‐parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application‐specific integrated circuit and field‐programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.     

Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays (FPGAs), thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array (FPGA) electronic design automation (EDA) tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.     

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization for droplet-based microfluidic arrays. We first formulate the test planning problem and prove that it is NP-hard. We then describe an optimization method based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-hard nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, the heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost. This research was supported in part by the National Science Foundation under grant number IIS-0312352. A preliminary version of this paper appeared in Proc. European Test Symposium. pp. 72–77, 2004 Fei Su received the B.E. and the M.S. degrees in automation from Tsinghua University, Beijing, China, in 1999 and 2001, respectively, and the M.S. degree in electrical and computer engineering from Duke University, Durham, NC, in 2003. He is now a Ph.D. candidate in electrical and computer engineering at Duke University. His research interests include design and testing of mixed-technology microsystems, electronic design automation, mixed-signal VLSI design, MEMS modeling and simulation. Sule Ozev received her B.S. degree in Electrical Engineering at Bogazici University in 1995, and her M.S. and Ph.D. degrees in Computer Science and Engineering at University of California, San Diego in 1998 and 2002 respectively. Since 2002, she has been a faculty member at Duke University, Electrical and Computer Engineering Department. Her research interests include RF circuit analysis and testing, process variability analysis, and mixed-signal testing. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Associate Professor of Electrical and Computer Engineering at Duke University. Dr Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award. His current research projects include: design and testing of system-on-chip integrated circuits; design automation of microfluidics-based biochips; microfluidics-based chip cooling; distributed sensor networks. Dr Chakrabarty has authored three books Microelectrofluidic Systems: Modeling and Simulation (CRC Press, 2002), Test Resource Partitioning for System-on-a-Chip (Kluwer, 2002), and Scalable Infrastructure for Distributed Sensor Networks (Springer, 2005) 3/4 and edited the book volume SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (Kluwer 2002). He has published over 200 papers in journals and refereed conference proceedings, and he holds a US patent in built-in self-test. He is a recipient of best paper awards at the 2005 IEEE International Conference on Computer Design and 2001 IEEE Design, Automation and Test in Europe (DATE) Conference. He is also a recipient of the Humboldt Research Fellowship, awarded by the Alexander von Humboldt Foundation, Germany. Dr Chakrabarty is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and System I, ACM Journal on Emerging Technologies in Computing Systems, and an Editor of Journal of Electronic Testing: Theory and Applications (JETTA). He a member of the editorial board for Sensor Letters and Journal of Embedded Computing and he serves as a subject area editor for the International Journal of Distributed Sensor Networks. He has also served as an Associate Editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. He is a senior member of IEEE, a member of ACM and ACM SIGDA, and a member of Sigma Xi. He serves as Vice Chair of Technical Activities in IEEE’s Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops. He served as the Program Co-Chair for the 2005 IEEE Asian Test Symposium.     

扬声器线阵列测量技术(待续)

有关扬声器线阵列测量目前并无统一的规范及方法。介绍了现有扬声器线阵列的测量技术及方法。指出在实验室环境下依据少量单元的声学测量预测扬声器大阵列声学辐射特性是未来研究的趋势。     

An 88 nm gate-length In_(0.53)Ga_(0.47)As/In_(0.52)Al_(0.48)As InP-based HEMT with f_(max) of 201 GHz

正An 88 nm gate-length In_(0.53)Ga_(0.47)As/In_(0.52)Al_(0.48)As InP-based high electron mobility transistor (HEMT) was successfully fabricated with a gate width of 2×50μm and source-drain space of 2.4μm.The T-gate was defined by electron beam lithography in a trilayer of PMMA/A1/UⅧ.The exposure dose and the development time were optimized,and followed by an appropriate residual resist removal process.These devices also demonstrated excellent DC and RF characteristics:the extrinsic maximum transconductance,the full channel current, the threshold voltage,the current gain cutoff frequency and the maximum oscillation frequency of the HEMTs were 765 mS/mm,591 mA/mm,-0.5 V,150 GHz and 201 GHz,respectively.The HEMTs are promising for use in millimeter-wave integrated circuits.     

薄栅氧化层斜坡电压TDDB寿命评价

随着超大规模集成电路的不断发展，薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。文章着重于薄栅氧化层TD-DB可靠性评价的斜坡电压试验方法的研究，基于斜坡电压实验，提取模型参数，分别利用线性场模型和定量物理模型，外推出工作电压下栅氧化层的寿命。通过分析斜坡电压实验时氧化层的击穿过程，提出斜坡电压实验时利用统一模型外推栅氧化层的寿命比较合适。     

采用基本门单元完全测试矢量的测试生成算法

文章介绍了一种采用基本逻辑门单元的安全测试矢量集生成测试矢量的方法，该方法可以将搜索空间限制在2(n 1）种组合内。它采用故障支配和故障等效的故障传播、回退等技术，建立了一套从局部到全局的测试生成新方法。同时，利用基本门单元安全测试矢量的规律性，可以实现最小的内存容量要求。在一些基准电路的应用实例中，得到了满意的结果。     

Combined probabilistic testability calculation and compact test generation for PLAs

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.¹ This work was done while B. Reppen was with the Norwegian Institute of Technology.     

The influence of oxidation-sirtl etch condition on the stacking fault generation in (111) silicon wafers

The successive oxidation-Sirtl etch technique has been investigated to evaluate the perfection of silicon crystals by detecting extrinsic stacking faults produced during oxidation. Experiments were performed in (111) epitaxial wafers. Measured densities of stacking faults were found to epend on the conditions of thermal oxidation, and stacking fault densities were a maximum at an oxidation temperature of around 1100°C. The stacking fault densities were reduced appreciably when epitaxial wafers were chemically etched to remove several tens of microns prior to the test. The generation of stacking faults is thought to occur by heterogeneous nucleation due to a very small amount of unidentified impurity found in epitaxial crystals.     

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems.     

T形栅In0.52Al0.48 As／In0.6Ga0.4As MHEMTs功率器件

利用电子束光刻技术制备了200nm栅长GaAs基T型栅InAlAs/InGaAs MHEMT 器件.该GaAs基MHEMT器件具有优越的直流、高频和功率性能,跨导、饱和漏电流密度、阈值电压、电流增益截止频率和最大振荡频率分别达到510mS/mm, 605mA/mm, -1.8V, 138GHz 和78GHz. 在8GHz下,输入功率为-0.88(2.11)dBm时,输出功率、增益、PAE、输出功率密度分别为14.05(13.79)dBm,14.9(11.68)dB,67.74 (75.1)%,254(239)mW/mm,为进一步研究高性能GaAs基MHEMT功率器件奠定了基础.     

基于FPGA NiosⅡ的信号发生器设计

介绍一种应用Nios Ⅱ嵌入式处理器的可编程片上系统(system-on-a programmable-chip,简称SOPC)技术来实现信号发生器的设计方案.该系统以Altera公司的Cyclone系列现场可编程门阵列(FPGA)为数字平台,将微处理器、总线、存储器和I/O接口等硬件设备集中在一片FPGA上,并利用数字调制技术使系统得到了正弦波、方波和三角波等.通过FPGA中双口RAM的数据读写产生波形.再充分利用片上资源,提高系统的精确度、稳定性和抗干扰性能.     

Optimized FPGA-based elliptic curve cryptography processor for high-speed applications

In this paper, we introduce an FPGA-based processor for elliptic curve cryptography on Koblitz curves. The processor targets specifically to applications requiring very high speed. The processor is optimized for performing scalar multiplications, which are the basic operations of every elliptic curve cryptosystem, only on one specific Koblitz curve; the support for other curves is achieved by reconfiguring the FPGA. We combine efficient methods from various recent papers into a very efficient processor architecture. The processor includes carefully designed processing units dedicated for different parts of the scalar multiplication in order to increase performance. The computation is pipelined providing simultaneous processing of up to three scalar multiplications. We provide experimental results on an Altera Stratix II FPGA demonstrating that the processor computes a single scalar multiplication on average in and achieves a throughput of 235,550 scalar multiplications per second on NIST K-163.     

栅氧化层TDDB可靠性评价试验及模型参数提取

采用恒定电压和恒定电流试验方法对20nm栅氧化层进行了TDDB可靠性评价试验，并完成了1／E模型参数提取，给出了恒定电流应力下描述氧化层TDDB退化的统计模型，较好地解释了试验结果。     

FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

This paper presents the design optimization of fully pipelined architectures for area-time-power-efficient implementation of finite impulse response (FIR) filter. The architectures are designed to obtain a suitable area-time tradeoff. Analysis of the performance of different filter orders and different address lengths of partial tables indicate the choice of four input partial tables presents the best of area-time-power-efficient realizations of FIR filter compared with the existing LUT-less DA-based implementations of FIR filters in both high-speed and medium-speed. Moreover, a number of further experiments not only shows the pipeline register’s significant influence to the maximum frequency of the FIR filters but also indicates it also has area usage. Final experiment shows that with the help of using pipeline register, the choice of 4-bits-per-clock (4BPC) of the architecture for word-length N=8 with four input partial table yields the best cost-effective when comparing with other different cases in both high-speed and medium-speed implementations.     

随机数发生器检测与设计

随机数常作为密钥、初始化向量或密码协议中的时变参数,在密码应用中起到非常重要的作用。根据密码应用对随机性的要求,随机数生成器的输出序列必须满足随机性和不可预测性要求。文中分析了随机数生成器和伪随机数生成器两种生成器模型,给出了常用的随机性检测方法,以及可能的安全攻击方法,最后提出了一种随机性检测新方法。该方法基于输出样本的每比特的信息熵估计,可用于随机数发生器设计过程中的随机性评估。