Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I_on), off-current (I_off), subthreshold swing (S), and I_on/I_off ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f_T) and maximum oscillation frequency (f_max) on gate–drain capacitance (C_gd) with the underlapping were investigated as the gate length (L_gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.     

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET

The favorable electrostatic potential and tunneling underneath the overall gate region, which prevents legitimate source to drain tunneling, controllability over the gate is assisted in vertical TFET configurations. An L-TFET (L-shaped Tunneling Field-Effect Transistor) has a larger tunneling length than a veritable TFET. As a consequence, the current in the on-state (I_on) has gotten better. The increased ambipolar current and low I_on/I_off ratio of L-TFET will need to be tuned for low-power and high-frequency functionality. On the other hand, significantly worse switching performance and distortions may lead to a weak robust device. By establishing a high-k gate oxide-based drain underlap region with dual gate, this study is dedicated to ameliorating the I_on/I_off by subverting ambipolar behavior. To investigate the impact of height of second gate (H_gate2) and work-function of this (WF_gate2), EBD (Energy Band Diagram), electric field distribution in X and Y direction, potential and recombination rate are examined under various conditions. Which leads to enhanced DC/RF and linearity performance. Along with this, Current-Voltage characteristics, DC/RF, and linearity performance Figure of Merits (FOMs) also investigated the assessment of variation of H_gate2 and WF_gate2, and it is optimized for the better suppression of I_ambi (ambipolar current) with a steep slope in transfer characteristics. In addition to that, Current-voltage statistics (I_ds − V_gs), DC/RF, and linearity efficiency FOMs were being used to assess the influence of changing the H_gate2 and WF_gate2, which was modulated for greater I_ambi suppression (ambipolar current) with improved SS and V_th for the proposed device.     

Chemical bath deposition of CdS channel layer for fabrication of low temperature-processed thin-film-transistors

～66 nm thick CdS film with a hexagonal structure was uniformly generated via a low temperature-processed chemical bath deposition at 80 °C using a complexing agent of ethylenediaminetetraacetic acid and its crystal structure, surface morphology, optical transmittance, and Raman scattering property were measured. Grown CdS film was used as a channel layer for the fabrication of bottom-gate, top-contact thin-film-transistor (TFT). The TFT device with 60 °C-dried channel layer exhibited a poor electrical performance of on-to-off drain current ratio (I_on/I_off) of 5.1 × 10³ and saturated channel mobility (μ_sat) of 0.10 cm²/Vs. However, upon annealing at 350 °C, substantially improved electrical characteristics resulted, showing I_on/I_off of 5.9 × 10⁷ and μ_sat of 5.07 cm²/Vs. Furthermore, CdS channel layer was chemically deposited in an identical way on a transparent substrate of SiN_x/ITO/glass as part of transparent TFT fabrication, resulting in I_on/I_off of 5.8 × 10⁷ and μ_sat of 2.50 cm²/Vs.     

Symmetric tunnel field-effect transistor (S-TFET)

A novel heterojunction symmetric tunnel field-effect transistor (S-TFET) has been proposed and investigated, for the first time, in order to address the inborn technical challenges of the conventional p-i-n TFET (i.e., asymmetric TFET). With a band-to-band tunneling process between the germanium source/drain region and the silicon channel region, the theoretical limit of the subthreshold slope (SS) can be overcome (i.e., SS ∼ 45 mV/decade). The bidirectional current flow in the S-TFET is implemented with a p-n-p structure. And better performance in the S-TFET is achieved with a thin silicon-pad layer below the source/drain regions. The effects of source/drain/channel doping concentration and thickness on the performance of the device are investigated in order to create an S-TFET design guideline. In the future, the S-TFET will be one of the promising device structures for ultra-low-power applications, especially in integrated circuits that operate with a half-volt power supply voltage.     

The effect of post-metal annealing on the electrical performance and stability of two-step-annealed solution-processed In2O3 thin film transistors

In this work, solution-processed indium oxide (In₂O₃) thin film transistors (TFTs) were fabricated by a two-step annealing method. The influence of post-metal annealing (PMA) temperatures on the electrical performance and stability is studied. With the increase of PMA temperatures, the on-state current and off-state current (I_on/I_off) ratio is improved and the sub-threshold swing (SS) decreased. Moreover, the stability of In₂O₃ TFTs is also improved. In all, In₂O₃ TFT with post-metal annealing temperature of 350°С exhibits the best performance (a threshold voltage of 4.75 V, a mobility of 13.8 cm²/V, an I_on/I_off ratio of 1.8 × 10⁶, and a SS of 0.76 V/decade). Meanwhile, the stability under temperature stress (TBS) and positive bias stress (PBS) also show a good improvement. It shows that the PMA treatment can effectively suppress the interface trap and bulk trap and result in an obviously improvement of the In₂O₃ TFTs performance.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

Extraction of density-of-states in amorphous InGaZnO thin-film transistors from temperature stress studies

The instability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with different active layer thicknesses under temperature stress has been investigated through using the density-of-states (DOS). Interestingly, the a-IGZO TFT with 22 nm active layer thickness showed a better stability than the others, which was observed from the decrease of interfacial and semiconductor bulk trap densities. The DOS was calculated based on the experimentally-obtained activation energy (E_A), which can explain the experimental observations. We developed the high-performance Al₂O₃ TFT with 22 nm IGZO channel layer (a high mobility of 7.4 cm²/V, a small threshold voltage of 2.8 V, a high I_on/I_off 1.8 × 10⁷, and a small SS of 0.16 V/dec), which can be used as driving devices in the next-generation flat panel displays.     

A novel double-recessed 4H-SiC MESFET with partly undoped space region

In this paper, a novel double-recessed 4H-SiC metal semiconductor field effect transistor (MESFET) with partly undoped space region (DRUS-MESFET) is introduced. The key idea in this work is to improve the DC and RF characteristics of the device by introducing an undoped space region. Using two-dimensional and two-carrier device simulation, we demonstrate that breakdown voltage (V_BR) increases from 109 V in conventional double recessed MESFET (DR-MESFET) structure to 144.5 V in the DRUS-MESFET structure due to the modified channel electric field distribution of the proposed structure. The maximum output power density of the DRUS-MESFET structure is about 25.4% larger than that of the DR-MESFET structure. Furthermore, lower gate-drain capacitance (C_GD), higher cut-off frequency (f_T), larger maximum available gain (MAG), and higher maximum oscillation frequency (f_max) are achieved for the DRUS-MESFET structure. The results show that the f_max and f_T of the proposed structure improve 95.6% and 13.07% respectively, compared with that of the DR-MESFET structure. Also, the MAG of the DRUS-MESET is 4.5 dB higher than that of the DR-MESFET structure at 40 GHz. The results show that the DRUS-MESFET structure has superior electrical characteristics and performances in comparison with the DR-MESFET structure.     

Synthesis,spectral characterization of CuPcF16 and its application in organic thin film transistors using p-6p as inducing layer

An air-stable n-channel semiconductor material, CuPcF₁₆, was synthesized in a slightly modified procedure and characterized by infrared (IR), X-ray diffraction (XRD), UV–vis and fluorescence spectra. CuPcF₁₆ showed a monomer characteristic in THF and pyridine while exhibited an aggregation property in DMF. The CuPcF₁₆/p-6p (CuPcF₁₆ on p-6p) organic thin film transistors (OTFTs) using CuPcF₁₆ as an active layer and p-6p as an inducing layer was fabricated by the physical vapor deposition technique. Charge carrier field-effect mobility (μ), I_on/I_off and threshold voltage (V_T) of the CuPcF₁₆/p-6p OTFTs were 0.07 cm²/V s, 10⁵ and 5.28 V, respectively. The charge mobility of the OTFTs was two or even three times higher than that of the conventional single layer CuPcF₁₆-based OTFTs. The improved performance was attributed to the introduction of p-6p to form a highly oriented and continuous film of CuPcF₁₆ with the molecular π–π conjugated direction parallel to the substrate.     

Investigation of enhancement mode HfO2 insulated N-polarity GaN/InN/GaN/In0.9Al0.1N heterostructure MISHEMT for high-frequency applications

In this paper, we examined normally-OFF N-polar InN-channel Metal insulated semiconductor high-electron mobility transistors (MISHEMTs) device with a relaxed In_0.9Al_0.1N buffer layer. In addition, the enhancement-mode operation of the N-polar structure was investigated. The effect of scaling in N-polar MISHEMT, such as the dielectric and the channel thickness, alter the electrical behavior of the device. We have achieved a maximum drain current of 1.17 A/mm, threshold voltage (V_T) =0.728 V, transconductance (g_m) of 2.9 S mm⁻¹, high I_ON/I_OFF current ratio of 3.23×10³, lowest ON-state resistance (R_ON) of 0.41 Ω mm and an intrinsic delay time (τ) of 1.456 Fs along with high-frequency performance with f_t/ f_max of 90 GHz/109 GHz and 180 GHz/260 GHz for T_CH =0.5 nm at V_ds =0.5 V and 1.0 V. The numerically simulated results of highly confined GaN/InN/GaN/In_0.9Al_0.1N heterostructure MISHEMT exhibits outstanding potential as one of the possibility to replace presently used N-polar MISHEMTs for delivering high power density and frequency at RF/power amplifier applications.     

Harmonic RF carrier generation and broadband data upconversion using stimulated Brillouin scattering

We propose and experimentally demonstrate a harmonic radio frequency (RF) carrier generation and broadband data upconversion technique with single mode and single sideband (− SSB) modulation for radio-over-fiber (RoF) systems using stimulated Brillouin scattering (SBS). The optical carrier-to-sideband ratio (CSR) of the single mode and SSB modulated signal can be easily adjusted to achieve the best received sensitivity performance of the RoF system. By using this method, we successfully demonstrate generation of third-harmonic RF carrier at 32.625 GHz with f_LO of 10.875 GHz and upconversion of 1.25-Gb/s data to the RF carrier band. In addition, the data bandwidth is independent of the Brillouin gain profile. Finally, the transmission performance of the RoF downlink system is examined.     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

Organic/inorganic interfaced field-effect transistor properties with a novel organic semiconducting material

A novel 1,3,4-oxadiazole-substituted benzo[b]triphenylene was synthesized by three-step synthetic procedure and OFET device design was successfully designed after theoretical calculations made using Gaussian software. For investigating the field-effect properties of designed organic electronic device, a SiO₂ (300 nm) was thermally grown on p-Si wafer at 1000 °C as a dielectric layer and gate, source and drain contacts have been deposited using Au metal with physical vapour deposition. 1,3,4-Oxadiazole-substituted benzo[b]triphenylene was spin coated on the source and drain electrodes of our device, forming organic/inorganic interfaced field-effect transistors. Surface morphology and thin film properties were investigated using AFM. All electrical measurements were done in air ambient. The device showed a typical p-type channel behaviour with increasing negative gate bias voltage values. Our results have surprisingly shown that the saturation regime of this device has high mobility (μ_FET), excellent on/off ratio (I_on/I_off), high transconductance (g_m) and a small threshold voltage (V_Th). The values of μ_FET, I_on/I_off, g_m and V_Th were found as 5.02 cm²/Vs, 0.7 × 10³, 5.64 μS/mm and 1.37 V, respectively. These values show that our novel organic material could be a potential candidate for organic electronic device applications in the future.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

Utilization of surface plasmon resonance of Au/Pt nanoparticles for highly photosensitive ZnO nanorods network based plasmon field effect transistor

Hydrothermally processed highly photosensitive ZnO nanorods based plasmon field effect transistors (PFETs) have been demonstrated utilizing the surface plasmon resonance coupling of Au and Pt nanoparticles at Au/Pt and ZnO interface. A significantly enhanced photocurrent was observed due to the plasmonic effect of the metal nanoparticles (NPs). The Pt coated PFETs showed I_on/I_off ratio more than 3 × 10⁴ under the dark condition, with field-effect mobility of 26 cm² V⁻¹ s⁻¹ and threshold voltage of −2.7 V. Moreover, under the illumination of UV light (λ = 350 nm) the PFET revealed photocurrent gain of 10⁵ under off-state (−5 V) of operation. Additionally, the electrical performance of PFETs was investigated in detail on the basis of charge transfer at metal/ZnO interface. The ZnO nanorods growth temperature was preserved at 110 °C which allowed a low temperature, economical and simple method to develop highly photosensitive ZnO nanorods network based PFETs for large scale production.     

Improved 4H–SiC MESFET with double source field plate structures

An improved 4H–SiC power MESFET with double source field plates (DSFP) for high-power applications is proposed (DSFP-MESFET). The DSFP structure significantly modifies the electric field in the drift layer. The influence of the DSFP structure on saturation current, breakdown voltage (V_b), and small-signal characteristics of the DSFP-MESFET were studied by numerical device simulation. The V_b of 359 V is obtained for the DSFP-MESFET compared to 301 V of the conventional source field plate MESFET (LSFP-MESFET). Hence, the maximum output power density of 24.7 and 21.8 W/mm are achieved for the DSFP-MESFET and LSFP-MESFET, respectively, which means 13% improvement for the proposed device. Also, the cut-off frequency (f_T) of 24.5 and the maximum oscillation frequency (f_max) of 89.1 GHz for the 4H–SiC DSFP-MESFET are obtained compared to 23.1 and 85.3 GHz for that of the LSFP-MESFET structure, respectively. The DSFP-MESFET shows a superior maximum stable gain (MSG) exceeding 23.3 dB at 3.1 GHz, which is presenting the potential of the proposed device for high-power operations.     

Pilot Study: Understanding the Effects of Voicing Intervention on HFCC Therapy in People with Cystic Fibrosis

The efficacy of High-Frequency Chest Compression (HFCC) airway clearance therapy is linked to the induced-peak expiratory airflow pulse (IPEF) at the patient's mouth. The authors' goal was to determine the conditions that yield the highest IPEF using HFCC running at 6 Hz in conjunction with voicing intervention. A pilot experimental study was conducted in a laboratory setting. Six adults with moderate to mild cystic fibrosis (CF) and 10 healthy adults participated. When the component characteristics of voicing were disregarded in data analysis of four conditions, voicing only intervention (V₁I₀), HFCC only intervention (V₀I₁), voicing intervention and HFCC intervention combinations (V₁I₁) and nonintervention (V₀I₀), V₀I₁ had significantly higher (P < 0.0001) IPEF. Data analyses of 64 separate voicing component characteristics, frequency (×4), amplitude (×4), and rhythm (×2) of voicing intervention, in addition to absence and presence of HFCC intervention (V₁I₀ and V₁I₁), were examined. One condition in V₁I₀ had significantly higher (P < 0.000001) IPEF than other conditions in V₁I₀ and V₁I₁ in both experimental and control groups. Based on these findings, V₁I₁ may yield higher IPEF than V₀I₁. One condition of amplitude component of voicing and one condition of rhythm component of voicing had significantly higher (P < 0.0001) IPEF than other conditions of amplitude and rhythm components in both CF and control subjects. Analysis of this combined condition of V₁I₁ showed that this specific condition of V₁I₁ had significantly higher (P < 0.000001) IPEF than any other conditions in V₁I₁ and V₀I₁.     

Effect of Ge doping on the electrical properties of amorphous Zn–Sn–O thin films

We report the effect of germanium doping on the active layer of amorphous Zinc–Tin-Oxide (a-ZTO) thin film transistor (TFT). Amorphous thin film samples were prepared by RF magnetron sputtering using single targets composed of Zn₂Ge_0.05Sn_0.95O₄ and Zn₂SnO₄ with variable oxygen contents in the sputtering gases. In comparison with undoped, Ge-doped a-ZTO films exhibited five order of magnitude lower carrier density with a significantly higher Hall-mobility, which might be due to suppressed oxygen vacancies in the a-ZTO lattice since the Ge substituent for the Sn site has relatively higher oxygen affinity. Thus, the bulk and interface trap densities of Ge-doped a-ZTO film were decreased one order of magnitude to 7.047 × 10¹⁸ eV⁻¹cm⁻³ and 3.52 × 10¹¹ eV⁻¹cm⁻², respectively. A bottom-gate TFT with the Ge-doped a-ZTO active layer showed considerably improved performance with a reduced SS, positively shifted V_th, and two orders of magnitude increased I_on/I_off ratio, attributable to the doped Ge ions.