Tuning the contact resistance in organic thin-film transistors with an organic-inorganic hybrid interlayer

We demonstrated the tunable contact resistance in pentacene thin film transistor (TFT) by inserting an organic-inorganic hybrid interlayer between Au electrode and pentacene layer. The contact resistance of pentacene-TFT varies with concentration of pentacene-TFT varies with concentration of MoO_x in organic-inorganic hybrid interlayer. MoO_x in organic-inorganic hybrid interlayer. The contact resistance of the device with 55 wt% MoO_x doped pentacene interlayer is about 7.8 times smaller than that of device without interlayer at the gate voltage of −20 V. Comparing the properties of pentacene-TFT without interlayer, the performance of the pentacene-TFT with 55 wt% MoO_x doped pentacene was significantly improved: saturation mobility increased from 0.39 to 0.87 cm²/V s, threshold voltage reduced from −21.3 to −7.2 V, and threshold swing varied from 3.75 to 1.39 V/dec. Our results indicated that the organic-inorganic hybrid interlayer is an effective way to improve the performance of p-channel OTFTs.     

SiOx interlayer to enhance the performance of InGaZnO-TFT with AlOx gate insulator

We have fabricated indium–gallium–zinc (IGZO) thin film transistor (TFT) using SiO_x interlayer modified aluminum oxide (AlO_x) film as the gate insulator and investigated their electrical characteristics and bias voltage stress. Compared with IGZO-TFT with AlO_x insulator, IGZO-TFT with AlO_x/SiO_x insulator shows superior performance and better bias stability. The saturation mobility increases from 5.6 cm²/V s to 7.8 cm²/V s, the threshold voltage downshifts from 9.5 V to 3.3 V, and the contact resistance reduces from 132 Ωcm to 91 Ωcm. The performance improvement is attributed to the following reasons: (1) the introduction of SiO_x interlayer improves the insulator surface properties and leads to the high quality IGZO film and low trap density of IGZO/insulator interface. (2) The better interface between the channel and S/D electrodes is favorable to reduce the contact resistance of IGZO-TFT.     

Interfacial electronic structure of molybdenum oxide on the fullerene layer,a potential hole-injecting layer in inverted top-emitting organic light-emitting diodes

The interfacial electronic structures of molybdenum oxide (MoO_x) deposited on fullerene (C₆₀) which could be used as a hole-injecting layer in inverted top-emitting organic light-emitting diodes (TE-OLEDs) were investigated by photoemission spectroscopy. The hole-injecting barrier height (Φ_B^h) at each interface investigated by an ultraviolet photoemission spectroscopy was reduced to from 1.4 to 0.1 eV as the thickness of MoO_x (Θ_MoOx) was increased from 0.1 to 5.0 nm on C₆₀. In these interface system, the sign of vacuum-level shift, highest occupied molecular orbital (HOMO)-level shift, and core-level shifts were all positive indicating that the interface mechanism is attributed to the work-function differences due to a band bending at these interfaces. Moreover, the near-edge X-ray absorption fine structure spectra at carbon K-edge did not show any structural modification as well as any chemical reaction at the MoO_x-on-C₆₀ interfaces when Θ_MoOx was changed on C₆₀. From these results, the inverted TE-OLED with C₆₀ (5.0 nm)/MoO_x (5.0 nm) showed the power efficiency of 1.7 lm/W at a luminance of about 1000 cd/m² and the maximum luminance of about 76.000 cd/m² at the bias voltage of 11.0 V. It exhibited the highest performance among the inverted TE-OLEDs fabricated as a function of MoO_x thickness from 0 to 5.0 nm.     

Study on characteristics of a double-conductible channel organic thin-films transistor with an ultra-thin hole-blocking layer

The properties of top-contact organic thin-film transistors (TC-OTFTs) using ultra-thin 2, 9-dimethyl-4, 7-diphenyl-1, 10-phenanthroline (BCP) as a hole-blocking interlayer have been improved significantly and a BCP interlayer was inserted into the middle of the pentacene active layer. This paper obtains a fire-new transport mode of an OTFT device with double-conductible channels. The accumulation and transfer of the hole carriers are limited by the BCP interlayer in the vertical region of the channel. A huge amount of carriers is located not only at the interface between pentacene and the gate insulator, but also at the two interfaces of pentacene/BCP interlayer and pentacene/gate insulator, respectively. The results suggest that the BCP interlayer may be useful to adjust the hole accumulation and transfer, and can increase the hole mobility and output current of OTFTs. The TC-OTFTs with a BCP interlayer at V_DS=-20~V showed excellent hole mobility μ_FE and threshold voltage V_TH of 0.58~cm²/(V\cdots) and --4.6~V, respectively.     

Improving the electrical performance of HfInZnO-TFTs by introducing a thin ITO interlayer

We have fabricated hafnium–indium–zinc-oxide (HfInZnO) thin film transistors (TFT) with indium–tin-oxide (ITO) interlayer. Compared with conventional HfInZnO-TFT, the electrical performance and bias stability of HfInZnO-TFTs with ITO interlayer are improved. HfInZnO-TFT with 4-nm-thick ITO interlayer shows a high mobility of 7.2 cm²/V s, a low threshold voltage of 0.13 V and a better bias stability. The performance enhancement is attributed to a decrease in interface trap state and an increase in carrier concentration. It suggests that introducing ITO interlayer at the ALD Al₂O₃/HfInZnO interface is an effective way to improve the electrical performance and bias stability.     

4,4′,4″-三(N-3-甲基苯基-N-苯基氨基)三苯胺掺杂MoOx作为空穴传输层对有机太阳电池性能的影响

通过采用4,4′,4″-三(N-3-甲基苯基-N-苯基氨基)三苯胺 (m-MTDATA)掺入MoO_x作为器件的空穴传输层来提高酞菁铜(CuPc)/C₆₀小分子 有机太阳电池的效率. 采用真空蒸镀的方法制备了一系列器件, 其中结构为铟锡氧化物 (ITO)/m-MTDATA:MoO_x(3:1)(30 nm)/CuPc(20 nm)/C₆₀(40 nm)/4,7-二苯 基-1,10-菲罗啉 (Bphen)(8 nm)/LiF(0.8 nm)/Al(100 nm)的器件, 在AM1.5 (100 mW/cm²)模拟太阳光的照射条件下, 开路电压V_oc=0.40 V, 短路电流J_sc=6.59 mA/cm², 填充因子为0.55, 光电转换效率达1.46%, 比没有空穴传输层的器件ITO/CuPc(20 nm)/C₆₀(40 nm)/Bphen(8 nm)/LiF(0.8 nm)/Al(100 nm) 光电转换效率提高了38%. 研究表明, 加入m-MTDATA:MoO_x(3:1)(30 nm)空穴传输层减小了有机层和ITO电极之间的接触电阻, 从而减小了整个器件的串联电阻, 提高了器件的光电转换效率.     

Room-temperature and solution-processed vanadium oxide buffer layer for efficient charge injection in bottom-contact organic field-effect transistors

We introduce a room temperature and solution-processible vanadium oxide (VO_x) buffer layer beneath Au source/drain electrodes for bottom-contact (BC) organic field-effect transistors (OFETs). The OFETs with the VO_x buffer layer exhibited higher mobility and lower threshold voltages than the devices without a buffer layer. The hole mobility with VO_x was over 0.11 cm²/V with the BC geometry with a short channel length (10 μm), even without a surface treatment on SiO₂. The channel width normalized contact resistance was decreased from 98 kΩ cm to 23 kΩ cm with VO_x. The improved mobility and the reduced contact resistance were attributed to the enhanced continuity of pentacene grains, and the increased work function and adhesion of the Au electrodes using the VO_x buffer layer.     

Enhanced electrical properties of pentacene-based organic thin-film transistors by modifying the gate insulator surface

A reliable surface treatment for the pentacene/gate dielectric interface was developed to enhance the electrical transport properties of organic thin-film transistors (OTFTs). Plasma-polymerized fluorocarbon (CFx) film was deposited onto the SiO₂ gate dielectric prior to pentacene deposition, resulting in a dramatic increase of the field-effect mobility from 0.015 cm²/(V s) to 0.22 cm²/(V s), and a threshold voltage reduction from −14.0 V to −9.9 V. The observed carrier mobility increase by a factor of 10 in the resulting OTFTs is associated with various growth behaviors of polycrystalline pentacene thin films on different substrates, where a pronounced morphological change occurs in the first few molecular layers but the similar morphologies in the upper layers. The accompanying threshold voltage variation suggests that hole accumulation in the conduction channel-induced weak charge transfer between pentacene and CFx.     

Atomic layer deposited HfO2 based metal insulator semiconductor GaN ultraviolet photodetectors

A report on GaN based metal insulator semiconductor (MIS) ultraviolet (UV) photodetectors (PDs) with atomic layer deposited (ALD) 5-nm-thick HfO₂ insulating layer is presented. Very low dark current of 2.24 × 10⁻¹¹ A and increased photo to dark current contrast ratio was achieved at 10 V. It was found that the dark current was drastically reduced by seven orders of magnitude at 10 V compared to samples without HfO₂ insulating layer. The observed decrease in dark current is attributed to the large barrier height which is due to introduction of HfO₂ insulating layer and the calculated barrier height was obtained as 0.95 eV. The peak responsivity of HfO₂ inserted device was 0.44 mA/W at bias voltage of 15 V.     

Memory effect of pentacene field-effect transistors with embedded monolayer of semiconductor colloidal nano-dots

We demonstrate memory effect of pentacene-based field-effect transistors (FETs) in which CdSe/ZnS colloidal nano-dots (NDs) are embedded. The colloidal NDs were dispersed in chloroform, and spread over a water surface to form monolayer of NDs. Then, they were transferred onto a 30-nm-thick poly(methyl methacrylate) (PMMA) surface by horizontal lifting method, and a 30-nm-thick pentacene film was deposited as an active layer to fabricate FETs. The threshold voltage (V_th) was shifted by ∼10 V after a writing voltage of 70–100 V was applied to the gate electrode of the memory-FETs. On the other hand, such a large shift of V_th was not observed for reference pentacene-FETs without NDs. We consider that the large shift of V_th is due to electrons trapped in the NDs at the interface of pentacene and PMMA layers.     

Room-temperature fabrication of ultra-thin ZrOx dielectric for high-performance InTiZnO thin-film transistors

In this letter, indium–titanium–zinc–oxide thin-film transistors with zirconium oxide (ZrO_x) gate dielectric were fabricated at room temperature. In the devices, an ultra-thin ZrO_x layer was formed as the gate dielectric by sol–gel process followed by ultraviolet (UV) irradiation. The devices can be operated under a voltage of 4 V. Enhancement mode operations with a high field-effect mobility of 48.9 cm²/V s, a threshold voltage of 1.4 V, a subthreshold swing of 0.2 V/decade, and an on/off current ratio of 10⁶ were realized. Our results demonstrate that UV-irradiated ZrO_x dielectric is a promising gate dielectric candidate for high-performance oxide devices.     

Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm²/Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al₂O₃ dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (ΔV_th) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.     

Synthesis of Si nanoparticles with narrow size distribution by pulsed laser ablation

We synthesized Si nanoparticles by pulsed nanosecond-laser ablation. We applied a positive voltage bias during laser irradiation and effectively reduced size distribution. Scanning electron micrographs of samples showed the nanoparticles to be highly non-agglomerated. Si nanoparticles have the average diameter of 4–5 nm, the geometrical standard deviation of 1.35, and the density of 1.6 × 10¹²/cm². A MOS device showed excellent charge trap behavior with a flat-band voltage shift over 7 V, which can be applied for memory device applications.     

An organic electrophosphorescent device driven by all-organic thin-film transistor using photoacryl as a gate insulator

Organic electrophosphorescent devices have been intensively investigated for using in full-color flat-panel display. Since the quantum efficiency of electrophosphorescent device decreases rapidly as the luminance increases, it is desirable to operate the electrophosphorescent display with active matrix rather than passive matrix. Here we report the study of driving electrophosphorescent diode with all-organic TFT. We obtained the maximum power luminance that was obtained about 90 cd/m². Turn-on voltage is approximately 10 V. Field effect mobility, threshold voltage, and on–off current ratio in 0.5-μm thick gate dielectric layer were 0.13 cm²/V s, −7 V, and 10⁶ A/A. The structure of electrophosphorescent diode is ITO/TPD/BCP:Ir(ppy)₃/BCP/Alq₃/Li:Al/Al. In organic TFT, photoacryl is used as an insulator and pentacene as an active layer.     

Characteristics of pentacene organic thin film transistor with top gate and bottom contact

High performance pentacene organic thin film transistors (OTFT) were designed and fabricated using SiO₂ deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S--D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage V_TH was --2.75± 0.1V in 0---50V range, and that subthreshold slopes were 0.42± 0.05V/dec. The field-effect mobility (μ_EF) of OTFT device increased with the increase of V_DS, but the μ_EF of OTFT device increased and then decreased with increased V_GS when V_DS was kept constant. When V_DS was --50V, on/off current ratio was 0.48× 10⁵ and subthreshold slope was 0.44V/dec. The μ_EF was 1.10cm²/(V.s), threshold voltage was --2.71V for the OTFT device.     

对以并五苯和酞菁铜为不同有源层的有机薄膜晶体管特性研究

通过扫描电镜和X射线衍射对SiO₂衬底上生长并五苯和酞菁铜薄膜的表面形貌进行表征,并得到在SiO₂衬底上生长的并五苯薄膜是以岛状结构生长,其大小约为100nm,且薄膜有较好的结晶取向,呈多晶态存在. 酞菁铜薄膜则没有表现出明显的生长机理,其呈非晶态存在. 还对通过掩膜的方法制作得以酞菁铜和并五苯为有源层的顶栅极有机薄膜晶体管的特性进行了研究. 有源层的厚度为40nm,绝缘层SiO₂的厚度为250nm,器件的沟道宽长比(W/关键词： 有机薄膜晶体管 并五苯薄膜 酞菁铜薄膜 μ_EF)')" href="#">场效应迁移率(μ_EF)     

Ar ion milling of InSb for manufacturing single electron devices

Ar⁺ ion milling of InSb for manufacturing single electron devices was studied. It is shown that pyramidal structures (porous) are created on the (1 1 1) surface of InSb wafers by anisotropic etching. Also it was shown the axis of the pyramidal structure is a function of the angle of the Ar⁺ incident beam and does not depend on the energy of the beam. EDX measurement results show In_xO_y and Sb_xO_y were not created on the surface after milling process. FTIR measurement results show that the surface reflection was decreased and less than 0.3 V flat band voltage was seen in capacitance voltage measurement results. SEM images show that the etching has approximately vertical profile. Therefore the Ar⁺ milling technique can be used as a dry etching technique for manufacturing mesa and/or porous structures of InSb. Since the surface is porous and of near-pyramidal morphology, one can simulate the surface by a set of needles each of which is a nanometer-size capacitance (i.e. single electron device). We showed, the threshold voltage of this single electron device is 0.3 V approximately, and therefore it can be used for studying single-electron or Coulomb blockade effects.     

Low driving voltage in organic light-emitting diode using MoO3/NPB multiple quantum well structure in hole transport layer

Driving voltage of organic light-emitting diode (OLED) is lowered by employing molybdenum trioxide (MoO₃)/N, N'-bis(naphthalene-1-yl)-N,N'-bis(phe-nyl)-benzidine (NPB) multiple quantum well (MQW) structure in hole transport layer. For the device with double quantum well (DQW) structure of ITO/ [MoO₃ (2.5 nm)/NPB (20 nm)]₂/Alq₃(50 nm)/LiF (0.8 nm)/Al (120 nm)], the turn-on voltage is reduced to 2.8 V, which is lowered by 0.4 V compared with that of the control device (without MQW structures), the driving voltage is 5.6 V, which is reduced by 1 V compared with that of the control device at the 1000 cd/m². In this work, the enhancement of the injection and transport ability for holes could reduce the driving voltage for the device with MQW structure, which is attributed not only to the reducing energy barrier between ITO and NPB, but also to the forming charge transfer complex between MoO₃ and NPB induced by the interfacial doping effect of MoO₃.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

Structural and electrochemical properties of layered lithium nitridocuprates Li3 − xCuxN

We report a systematic study of the layered lithium nitridocuprates Li_3 ? xCu_xN with 0.1 ≤ x ≤ 0.39. The structural data obtained from experimental XRD patterns, Rietveld refinements and unit cell parameters calculation vs x, indicate that copper (I) substitute interlayer lithium ions in the parent nitride Li₃N to form the Li_3 ? xCu_xN compound without any Li vacancy in the Li₂N^? layer. Electrochemical results report Li insertion into the corresponding layered structures cannot take place in the 1.2/0.02 V voltage range as in the case of lithium into nitridonickelates and nitridocobaltates. However, in the initial charge process of Li_3 ? xCu_xN at 1.4 V leading to a specific capacity higher than 1000 mA h/g, the oxidation of copper and nitride ions is probably involved inducing a strong structural disordering process. As a consequence a new rechargeable electrochemical system characterized by discharge–charge potential of ≈ 0.3 V/1.2 V appears from the second cycle. Cycling experiments 0.02 V voltage/0.02 V range induce a complete destruction of the layered host lattice and the presence of Cu₃N in the charge state suggests a conversion reaction. The capacity recovered in the 1.4/0.02 V range practically stabilizes around 500 mA h/g after 20 cycles.