Enhanced electrical stability of flexible indium tin oxide films prepared on stripe SiO2 buffer layer-coated polymer substrates by magnetron sputtering

The electrical stability of flexible indium tin oxide (ITO) films fabricated on stripe SiO₂ buffer layer-coated polyethylene terephthalate (PET) substrates by magnetron sputtering was investigated by the bending test. The ITO thin films with stripe SiO₂ buffer layer under bending have better electrical stability than those with flat SiO₂ buffer layer and without buffer layer. Especially in inward bending text, the ITO thin films with stripe SiO₂ buffer layer only have a slight resistance change when the bending radius r is not less than 8 mm, while the resistances of the films with flat SiO₂ buffer layer and without buffer layer increase significantly at r = 16 mm with decreasing bending radius. This improvement of electrical stability in bending test is due to the small mismatch factor α in ITO-SiO₂, the enhanced interface adhesion and the balance of residual stress. These results indicate that the stripe SiO₂ buffer layer is suited to enhance the electrical stability of flexible ITO film under bending.     

Thin film transistors based on TiO2 fabricated by using radio-frequency magnetron sputtering

This study demonstrates that nanocrystalline TiO₂ thin films were deposited on ITO/glass substrate by radio-frequency magnetron sputtering. Field-emission scanning electron microscope (FE-SEM) and atomic force microscopic (AFM) images showed the morphology of TiO₂ channel layer with grain size and root-mean-square (RMS) roughness of 15 and 5.39 nm, respectively. TiO₂ thin-film transistors (TFTs) with sputter-SiO₂ gate dielectric layer were also fabricated. It was found that the devices exhibited enhancement mode characteristics with the threshold voltage of 7.5 V. With 8-μm gate length, it was also found that the I_on/off ratio and off-state current were around 1.45×10² and 10 nA, respectively.     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Improvement of electrical properties of silicon-based thin-film transistors by modifying technological fabrication processes

This paper is a review of technological process evolution associated to electrical performance improvement of silicon-based thin-film transistors (TFTs) that were performed mainly in the GM/IETR laboratory. The main objective in agreement with the fields of applications is to fabricate TFTs at a temperature low enough to be compatible with the substrates, glass substrates in a first place and flexible substrates in a second one, which implies several approaches. In fact, the electrical properties of the TFTs, mainly field-effect mobility of carriers in the channel, I _on/I _off drain current ratio, and subthreshold slope, are strongly dependent on the quality and the nature of the channel material, on the material quality and thus on the density of states at the interface with the gate insulator, and on the quality of the gate insulator itself. All the improvements are directly linked to all these aspects, which means an actual combination of the efforts. For the glass substrate, compatible technology processes such as deposition techniques, or solid phase, or laser crystallizations of active layers were studied and compared. The paper details all these approaches and electrical performances. In addition, some results about the use of a silicon–germanium compound as channel active layer and airgap transistors for which the insulator is released, complete the presentation of the evolution of the silicon-based TFTs during the last twenty years.     

Photoluminescence of Si from Si nanocrystal-doped SiO2/Si multilayered sample

A multilayered Si nanocrystal-doped SiO₂/Si (or Si-nc:SiO₂/Si) sample structure is studied to acquire strong photoluminescence (PL) emission of Si via modulating excess Si concentration. The Si-nc:SiO₂ results from SiO thin film after thermal annealing. The total thickness of SiO layer remains 150 nm, and is partitioned equally into a number of sublayers (N = 3, 5, 10, or 30) by Si interlayers. For each N-layered sample, a maximal PL intensity of Si can be obtained via optimizing the thickness of Si interlayer (or d_Si). This maximal PL intensity varies with N, but the ratio of Si to O is nearly a constant. The brightest sample is found to be that of N = 10 and d_Si = 1 nm, whose PL intensity is ∼5 times that of N = 1 without additional Si doping, and ∼2.5 times that of Si-nc:SiO₂ prepared by co-evaporating of SiO and Si at the same optimized ratio of Si to O. Discussions are made based on PL, TEM, EDX and reflectance measurements.     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Enhancement of giant magneto-impedance effect in Ni80Fe20/SiO2/Cu composite wires

Ni₈₀Fe₂₀/SiO₂/Cu composite wires of Cu core 60 μm in diameter and coated with layers of SiO₂ and Ni₈₀Fe₂₀ were prepared by RF magnetron sputtering. The influences of the insulator layer thickness, the measurement mode and the magnitude of the driving current on the giant magneto-impedance (GMI) effect were investigated. The results showed that there was an optimum thickness of the insulator layer and the driving current can influence the shape of the MI curve. Resonance enhancement of the GMI was found in the new measurement mode. The results are discussed by taking account of the electromagnetic interactions.     

Effect of buffer layer on thermochromic performances of VO2 films fabricated by magnetron sputtering

As a well-developed industrial fabricating method, magnetron sputtering technique has its distinct advantages for the large-scale production. In order to investigate the effect of buffer layer on the formation and thermochromic performances of VO₂ films, using RF magnetron sputtering method, we fabricated three kinds of buffer layers SiO₂, TiO₂ and SnO₂ on soda lime float-glass. Then according to the reactive DC magnetron sputtering method, VO₂ films were deposited. Due to the restriction of heat treatment temperature when using soda lime float-glass as substrates, dense rutile phase TiO₂ cannot be formed, leading to the formation of vanadium oxide compounds containing Na ions. When using SnO₂ as buffer layer, we found that relatively high pure VO₂ can be deposited more easily. In addition, compared with the effect of SiO₂ buffer layer, we observed an enhanced visible transparency, a decreased infrared emissivity, which should be mainly originated from the modified morphology and/or the hetero-structured VO₂/SnO₂ interface.     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

Enhancement of L10 ordered FePt by Pt buffer layer

L₁₀-ordered FePt thin films prepared by molecular-beam epitaxy on MgO (0 0 1) substrate at 320 °C with different thickness of Pt buffer layer have been investigated. The out-of-plane coercivity increases with increasing thickness of Pt buffer. The maximum values of the long-range order parameter and uniaxial magnetic anisotropy energy are 0.72 and 1.78×10⁷ erg/cm³, respectively, for films with 12 nm thick Pt buffer layer, where the c/a ratio (0.976) shows the minimum value. The reason for the enhancement in ordering is due to the proper lattice strains Pt buffer bestows on FePt layer, these strains are equal to the contraction in lattice parameter c and the expansion in a. Studies of angular-dependent coercivity revealed that the magnetization reversal behaviour shifts from a domain-wall motion dominated case towards a near rotational mode with increasing thickness of Pt buffer layer.     

Effect of buffer layer on VOx film fabrication by reactive RF sputtering

Vanadium oxide VO_x films were fabricated by RF magnetron sputtering on various metal buffer layers or silica glass substrates at a substrate temperature of 400 °C. V₂O₅ film was fabricated on a silica glass substrate, and VO₂ films were fabricated on V, W, Fe, Ni, Ti, and Pt metal buffer layers. The transition temperature of the sample on the V buffer layer was 68 °C and that on the W buffer layer was 53 °C. The VO₂ film was also fabricated on the V buffer layer by non-reactive sputtering using a V₂O₅ target at a substrate temperature of 400 °C.     

High temperature characteristics of ZnO-based MOS-FETs with a photochemical vapor deposition SiO2 gate dielectric

The authors report the fabrication of ZnO-based metal-oxide-semiconductor field effect transistors (MOSFETs) with a high quality SiO₂ gate dielectric by photochemical vapor deposition (photo-CVD) on a sapphire substrate. Compared with ZnO-based metal-semiconductor FETs (MESFETs), it was found that the gate leakage current was decreased to more than two orders of magnitude by inserting the photo-CVD SiO₂ gate dielectric between ZnO and gate metal. Besides, it was also found that the fabricated ZnO MOSFETs can achieve normal operation of FET, even operated at 150 °C. This could be attributed to the high quality of photo-CVD SiO₂ layer. With a 2 μm gate length, the saturated I_ds and maximum transconductance (G_m) were 61.1 mA/mm and 10.2 mS/mm for ZnO-based MOSFETs measured at room temperature, while 45.7 mA/mm and 7.67 mS/mm for that measured at 150 °C, respectively.     

Structure of Al2O3 thin layers synthesized on the silicon surface by atomic layer deposition

The distribution of the phase and chemical composition at an Al₂O₃/Si interface is studied by depth-resolved ultrasoft x-ray emission spectroscopy. The interface is formed by atomic layer deposition of Al₂O₃ films of various thicknesses (from several to several nanometers to several hundreds of nanometers) on the Si(100) surface (c-Si) or on a 50-nm-thick SiO₂ buffer layer on Si. L _2,3 bands of Al and Si are used for analysis. It is found that the properties of coatings and Al₂O₃/Si interfaces substantially depend on the thickness of the Al₂O₃ layer, which is explained by the complicated character of the process kinetics. At a small thickness of coatings (up to 10–30 nm), the Al₂O₃ layer contains inclusions of oxidized Si atoms, whose concentration increases as the interface is approached. As the thickness increases, a layer containing inclusions of metallic Al clusters forms. A thin interlayer of Si atoms occurring in an unconventional chemical state is found. When the SiO₂ buffer layer is used (Al₂O₃/SiO₂/Si), the structure of the interface and the coating becomes more perfect. The Al₂O₃ layer does not contain inclusions of metallic aluminum, does not vary with the sample thickness, and has a distinguished boundary with silicon.     

Giant magneto-impedance effect of magnetron sputtered Ni80Fe20/SiO2/Cu composite wires

In this work, Ni₈₀Fe₂₀/Cu and Ni₈₀Fe₂₀/SiO₂/Cu composite wires of Cu core 100 μm in diameter and coated with a layer of Ni₈₀Fe₂₀ were produced by RF magnetron sputtering. In order to obtain a uniform coating, the wires were spun during sputtering. The influences of the magnetic coating and insulator thickness on the GMI effect of the composite wires were investigated. The results showed that the film thickness has a significant effect on the magnitude and the optimum frequency of the GMI effect. After the addition of an insulator layer, the MI ratio of the composite wires was observed to change with varying thickness of the insulator layer. This observed trend was attributed to the interaction between the conductive layer and the high-permeability magnetic coating.     

Effects of interface on the dielectric properties of Ba0.6Sr0.4TiO3 thin film capacitors

Ba_0.6Sr_0.4TiO₃ thin films were deposited on Pt/SiO₂/Si substrate by radio frequency magnetron sputtering. High-resolution transmission electron microscopy (HRTEM) observation shows that there is a transition layer at BST/Pt interface, and the layer is about 7-8 nm thickness. It is found that the transition layer was diminished to about 2-3 nm thickness by reducing the initial RF sputtering power. X-ray photoelectron spectroscopy (XPS) depth profiles show that high Ti atomic concentration results in a thick interfacial transition layer. Moreover, the symmetry ν of ?_r-V curve of BST thin film is enhanced from 52.37 to 95.98%. Meanwhile, the tunability, difference of negative and positive remanent polarization (P_r), and that of coercive field (E_C) are remarkably improved.     

Investigation in the interface roughness of DC-sputtered Mo/B4C multilayer mirrors with variable layer pairs for 7-nm soft X-ray polarizers

The surface and interface roughness of Mo/B₄C multilayer mirrors for 7-nm soft X-ray polarizer with variable layer pairs (N = 50, 70, 90 and 110), fabricated by DC sputtering technique is investigated by atomic force microscopy and X-ray scattering and reflecting. The experimental results present that the surface and interface roughness of Mo/B₄C multilayer mirrors increase layer by layer from its substrate as its Mo layer thickness greater than 2 nm, and the roughness grown tendency could be characterized by a quadratic function.     

ZnO:Ag film growth on Si substrate with ZnO buffer layer by rf sputtering

ZnO buffer layers were deposited on n-Si (1 0 0) substrate by rf magnetron sputtering at a lower power of 40 W. Then Ag-doped ZnO (SZO) films were deposited on buffered and non-buffered Si at a higher sputtering power of 100 W. The effects of buffer layer on the structural, electrical and optical properties of SZO films were investigated. The three-dimensional island growth process of ZnO buffer layer was discussed. The energy band diagram of p-SZO/n-Si heterojunction was constructed based on Anderson's model. Results show the ZnO buffer layer leads to better properties of SZO film, including larger grain size, smoother surface, higher carrier mobility, better rectifying behavior, lower interface state density, and weaker deep-level emission. It is because the ZnO buffer layer effectively relaxes the partial stress induced by the large lattice mismatch between SZO and Si.     

Molecular control over Ag/p-Si diode by organic layer

Electrical transport properties of Ag metal-fluorescein sodium salt (FSS) organic layer-silicon junction have been investigated. The current-voltage (I-V) characteristics of the diode show rectifying behavior consistent with a potential barrier formed at the interface. The diode indicates a non-ideal I-V behavior with an ideality factor higher than unity. The ideality factor of the Ag/FSS/p-Si diode decreases with increasing temperature and the barrier height increases with increasing temperature. The barrier height (φ_b=0.98 eV) obtained from the capacitance-voltage (C-V) curve is higher than barrier height (φ_b=0.72 eV) derived from the I-V measurements. The barrier height of the Ag/FSS/p-Si Schottky diode at the room temperature is significantly larger than that of the Ag/p-Si Schottky diode. It is evaluated that the FSS organic layer controls electrical charge transport properties of Ag/p-Si diode by excluding effects of the SiO₂ residual oxides on the hybrid diode.     

Thickness measurement of a thin hetero-oxide film with an interfacial oxide layer by X-ray photoelectron spectroscopy

The general equation T_ove = L cos  θ ln(R_exp/R₀ + 1) for the thickness measurement of thin oxide films by X-ray photoelectron spectroscopy (XPS) was applied to a HfO₂/SiO₂/Si(1 0 0) as a thin hetero-oxide film system with an interfacial oxide layer. The contribution of the thick interfacial SiO₂ layer to the thickness of the HfO₂ overlayer was counterbalanced by multiplying the ratio between the intensity of Si⁴⁺ from a thick SiO₂ film and that of Si⁰ from a Si(1 0 0) substrate to the intensity of Si⁴⁺ from the HfO₂/SiO₂/Si(1 0 0) film. With this approximation, the thickness levels of the HfO₂ overlayers showed a small standard deviation of 0.03 nm in a series of HfO₂ (2 nm)/SiO₂ (2-6 nm)/Si(1 0 0) films. Mutual calibration with XPS and transmission electron microscopy (TEM) was used to verify the thickness of HfO₂ overlayers in a series of HfO₂ (1-4 nm)/SiO₂ (3 nm)/Si(1 0 0) films. From the linear relation between the thickness values derived from XPS and TEM, the effective attenuation length of the photoelectrons and the thickness of the HfO₂ overlayer could be determined.