峰值电流型PWM调制buck DC-DC的建模与仿真分析

针对目前直流转直流(DC-DC)变换器系统建模方法受限于实际电路的局限性,提出了一种新型的Cadence系统建模方法。利用Cadence工具及其理想元器件,建立脉宽调制(PWM)峰值电流型buck DC-DC的系统模型。为验证模型的性能,在旺宏0.5 μm BCD工艺条件下,用电路结构替换理想模型,得到电路系统,并将其与系统模型的仿真结果进行对比。仿真结果表明,以该系统模型为指导设计的buck DC-DC芯片在340 kHz工作频率下具有宽输出电压范围,并能提供2 A的大负载电流,从而验证了该设计方法的可行性。     

DC-DC降压变换器的滑模控制研究

为更快获得比较理想的直流输出电压,优化Buck变换器的动态性能,本文分析了一种滑模控制器控制的直流-直流降压变换器,推导了描述降压变换器的动态方程,并设计了滑模控制器。通过MATLAB/Simulink进行仿真,仿真结果表明,基于滑模控制的降压转换器对负载变化和输入电压变化的有效性和鲁棒性。     

降压PWM DC/DC开关稳压系统仿真分析

集成CMOS脉冲宽度调制开关电源系统因为高效率、高集成度等优点在通信、计算机系统方面被广泛应用.文中通过分析建立一个PWM DC/DC稳压系统的闭环响应传输函数,研究如何在瞬态响应速度和稳定性方面进行取舍;在此基础上用Matlab建立小信号模型仿真,并通过Hspice 实现仿真验证.     

Sliding mode control and stability analysis of buck DC-DC converter

This paper is proposed to deal with the voltage regulation of buck DC-DC converter based on sliding mode control (SMC) technology. A buck DC-DC converter with parasitic resistance is inherently a bilinear system possessing inevitable uncertainties, such as variable resistive load and input disturbance. First, the buck DC-DC converter is modified into an uncertain linear model. Then, SMC technology is adopted to suppress the input disturbance and reduce the effects from the load variation. In addition, the continuous conduction mode (CCM) for normal operation can be guaranteed by the design of sliding function. Finally, experimental results are included for demonstration.     

50 MHz dual-mode buck DC-DC converter

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS (BIAS current). A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18 μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.     

Novel topologies for DC-DC converter with PWM control

Two topologies for the buck converter are presented. The first converter consists of two active switches whereas the second converter, derived from the parent twoswitch converter, consists of only one active switch. The main feature of this new converter is the ability to operate at a constant switching frequency using a simple PWM control. The design of the gate circuit is simplified as there is only one switch. The converter has a good efficiency, as is proved by the experimental results. The operation of the parent two-switch converter, from which the new single-switch converter is derived, is also presented to gain insight into the design of the new converter.     

A PWM plus phase-shift control bidirectional DC-DC converter

A pulse-width modulation (PWM) plus phase-shift control bidirectional dc-dc converter is proposed. In this converter, PWM control and phase-shift control are combined to reduce current stress and conduction losses, and to expand ZVS range. The operation principle and analysis of the converter are explained, and ZVS condition is derived. A prototype of PWM plus phase-shift bidirectional dc-dc converter is built to verify the analysis.     

Zero-voltage-switching half-bridge DC-DC converter with modified PWM control method

Asymmetric control scheme is an approach to achieve zero-voltage switching (ZVS) for half-bridge isolated dc-dc converters. However, it is not suited for wide range of input voltage due to the uneven voltage and current components stresses. This paper presents a novel "duty-cycle-shifted pulse-width modulated" (DCS PWM) control scheme for half-bridge isolated dc-dc converters to achieve ZVS operation for one of the two switches without causing the asymmetric penalties in the asymmetric control and without adding additional components. Based on the DCS PWM control scheme, an active-clamp branch comprising an auxiliary switch and a diode is added across the isolation transformer primary winding in the half-bridge converter to achieve ZVS for the other main switch by utilizing energy stored in the transformer leakage inductance. Moreover, the auxiliary switch also operates at ZVS and zero-current switching (ZCS) conditions. Furthermore, during the off-time period, the ringing resulted from the oscillation between the transformer leakage inductance and the junction capacitance of two switches is eliminated owing to the active-clamp branch and DCS PWM control scheme. Hence, switching losses and leakage-inductance-related losses are significantly reduced, which provides the converter with the potential to operate at higher efficiencies and higher switching frequencies. The principle of operation and key features of the proposed DCS PWM control scheme and two ZVS half-bridge topologies are illustrated and experimentally verified.     

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.     

同步降压式DC-DC转换器的稳定性设计

DC-DC转换器因其相比于传统的线性稳压器具有较高的电源转换效率,而被广泛地应用到各种现代电子设备中。同时随着电源整流技术的不断进步,DC-DC转换器也正在从以肖特基二极管作为续流二极管的异步整流模式向同步整流模式转变。同步整流式DC-DC转换器具有极高的电源转换效率(可超过95%),是各种手持设备电源设计的首选。本文从分析同步降压式DC-DC转换器的闭环增益和相位曲线入手,研究了多种条件下如何实现同步降压式DC-DC转换器的稳定性设计。     

Robust control of parallel DC-DC buck converters by combiningintegral-variable-structure and multiple-sliding-surface control schemes

We develop a robust controller for parallel DC-DC buck converters by combining the concepts of integral-variable-structure and multiple-sliding-surface control. The advantages of the scheme are its simplicity in design, good dynamic response, robustness, ability to nullify the bus-voltage error and the error between the load currents of the converter modules under steady-state conditions, and ability to reduce the impact of very high-frequency dynamics due to parasitics on the closed-loop system. We describe a method for determining the region of existence and stability of the sliding manifolds for such parallel converters. The results show good steady-state and dynamic responses     

Design of high efficiency dual-mode buck DC-DC converter

A buck DC-DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current,and it can operate with an input range of 4.5 to 30 V.At light load current,the converter operates in skip mode.The converter enters PWM mode operation with increasing load current.It reduces the switching loss at light load and standby state,which results in prolonging battery lifetime and stand-by time.Meanwhile, externally adjustable soft-start minimizes the inru...     

On-chip CMOS current-sensing circuit for DC-DC buck converter

An on-chip CMOS current-sensing circuit for a DC-DC buck converter is presented. The circuit can measure the inductor current through sensing the voltage of the switch node during the converter on-state. By matching the MOSFETs, the achieved sense ratio is almost independent of temperature, model and supply voltage. The proposed circuit is suitable for low power DC-DC applications with high load current.     

一种宽范围可调的小型DC-DC降压变换器

提出了一种小型可调压DC-DC降压变换器的结构。主电路由MOSFET管、电感器及滤波电容器构成。通过PWM波控制,由于PWM波的驱动能力较差,设计驱动电路通过与PWM发生器一同控制MOSFET管的通断。通过改变PWM波的占空比来改变输出电压以达到可调压的目的。该降压变换器设计简单、经济适用、体积较小,输出电压可调。主要由主电路和驱动电路组成。该变换器适用于较低压工作场合,输入电压在5V至20V之间,输出电压在3V至18V之间。对电路的工作原理和结构进行了深入分析,并通过实物制作验证其可行性。     

A buck quadratic PWM soft-switching converter using a single activeswitch

High-switching frequency associated with soft commutation techniques is a trend in switching converters. Following this trend, a buck pulsewidth modulation (PWM) converter is presented. The DC voltage conversion ratio of this converter has a quadratic dependence on duty cycle, providing a large stepdown. This new buck quadratic PWM soft-single-switched converter, having only a single active switch, provides a high efficient operating condition for a wide load range at high-switching frequency. In order to illustrate the operating principle of this new converter, a detailed study including theoretical analysis, relevant equations and simulation, and experimental results is carried out     

Two-switch forward soft-switching PWM DC-DC power converter

A novel prototype is presented of a two-switch forward soft-switching PWM DC-DC power converter with reduced switching and conduction power losses, which can operate under two soft commutations of zero voltage and zero current of full bridge circuit topology     

一种具有动态零点补偿的电流模DC-DC降压型转换器

To achieve fast transient response for a DC-DC buck converter,an adaptive zero compensation circuit is presented.The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions.An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size.In addition,analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique.A currentmode DC-DC buck converter with the proposed structure has been implemented in a 0.35μm CMOS process,and the die size is only 800×1040μm~2.The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30μs for a load current variation from 100 mA to 1 A.     

一种峰值电流型降压DC-DC转换电路的设计

设计了一款基于SMIC 0.35 μmBCD工艺的降压型DC-DC转换芯片,主 要应用于大 功率宽输入范围的电源管理系统。采用峰值电流型PWM控制方式提供优良的负载调整特 性和抗输入电源扰动能力;在电流采样的输出端添加斜坡补偿模块消除峰值电流模式引起 的次谐波振荡问题;设计高增益、大带宽的电压反馈误差放大器以提供大的负载调整率并 提高负载的瞬态响应能力;设计高单位增益带宽的PWM控制器以满足高开关频率工作的 要求,同时提高转换效率。此外,加入了一系列保护模块以维持芯片的正常工作。系统仿 真结果表明:在10 V的输入电压范围内, 稳定输出5.5 V电压,开关频率为330 kHz, 额定输出电流为1.5 A,在输入范围内的转换效率均在80%以上,典型应用下转换效率高 达90%。     

一种新型软开关DC-DC PWM升压变换器设计

为提高转换效率并降低电源开关的电流应力,提出一种基于新型有源缓冲电路的PWM DC-DC升压变换器。该有源缓冲电路使用ZVT—ZCT软开关技术,分别提供了总开关ZVT开启及ZCT闭合、辅助开关ZCS开启及ZCT闭合。消除了总开关额外的电流及电压应力,消除了辅助开关电压应力,且有源缓冲电路的耦合电感降低了电流应力。另外,通过连续将二极管添加到辅助开关电路,防止来自共振电路的输入电流应力进入总开关。实验结果表明,相比传统的PWM变换器,新的DC-DC PWM升压变换器在满负荷时电流应力降低且总体效率能达到98.7%。     

Digitally controlled PWM buck converter employing counter and VCOs

Analog Integrated Circuits and Signal Processing - This paper describes a digitally controlled PWM (DCPWM) buck converter employing a counter and two Voltage Controlled Oscillators (VCOs) for...