Electron beam induced current investigations of active electrical defects in silicon due to reactive ion etching and reactive ion beam etching processes

Reactive ion etching and reactive ion beam etching are common tools for anisotropic etch processes in silicon microdevice fabrication; but, unfortunately, they also create radiation damage in the etched surface. We have studied the electrically active defects by measuring the recombination of carriers with the help of the electron beam induced current (EBIC) mode of a secondary electron microscope. We have measured the temperature behavior of the samples by annealing studies and the temperature dependent EBIC signal for several p-doped silicon wafers and obtained different shaped curves. Theoretical EBIC models developed with the assumption of a reduced net carrier concentration in the etched areas agree with our experimental results.     

Effects of heavy ion irradiation on ultra-deep-submicron partially-depleted SOI devices

The effects of the physical damages induced by heavy ion irradiation on the performance of partially-depleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance, and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design.     

Properties of buried SiC layers produced by carbon ion implantation in (100) bulk silicon and silicon-on-sapphire

Buried layers of SiC were formed in (100) single-crystal bulk silicon and silicon-on-sapphire by ion implantation of 125–180 keV, (0.56-1.00) × 10¹⁸ C/cm² at 30–40 μA/ cm² into samples held at 450-650° C. The as-implanted and 950° C annealed samples were characterized by differential infra-red absorbance and reflectance, Rutherford backscattering and channeling spectrometry, x-ray diffraction, four-point probe measurements, Dektak profilometry, I-V measurements, spreading resistance measurements and secondary ion mass spectrometry. Work done while affiliated with Rockwell International Corporation, Microelectronics Research & Development Center, 3370 Miraloma Avenue, Anaheim, CA 92803 and a Visiting Associate at the California Institute of Technology, Department of Applied Physics, Mail Code 116-81, Pasadena, CA 91125.     

Impact of bias conditions on performance degradation in SiGe HBTs irradiated by 10 MeV Br ion

Effects of bias conditions on 10 MeV Br ion irradiation were investigated in NPN SiGe HBTs. Pre- and post-radiation direct current (DC) characteristics, such as current gain, leakage current, Early voltage and neutral base recombination, were studied and used to quantify the dose tolerance to 10 MeV Br ion. Experiment results for different bias conditions were compared and discussed in detail. It is found that performance degradations are indeed bias dependent. The BE junction reversed-biased mode suffers the largest degradation and the case with BE junction forward-biased shows the smallest degradation. The underlying physical mechanisms are analyzed and investigated in present work. The injection annealing effect of displacement damage is found to be responsible for the different irradiation response of SiGe HBTs under three bias conditions.     

离子减薄诱发的Zr65Al7.5Ni10Cu17.5块状非晶晶化相的相变

用透射电子显微镜研究了锆基块状非晶合金晶化行为，对分别经双喷电解减薄加离子减薄和单纯双喷电解减薄制备的电镜样品进行观察分析，发现离子减薄会导致该合金晶化亚稳相的转变。     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

Characterization of defects in hydrogenated amorphous silicon devices using charge collection scanning electron microscopy

Electron-beam-induced current (EBIC) and secondary electron image (SEI) modes of a scanning electron microscope (SEM) are utilized for characterization of charge collection inhomogeneities in hydrogenated amorphous silicon devices. These inhomogeneities are due to such fabrication defects as substrate surface roughness, pin holes, blistering and lift-off. SEM observations are correlated with the electrical properties of the devices. Electronirradiation-induced damage in these devices is also investigated by measuring the EBIC time decay at continuous electron irradiation as a function of both the electron -beam energy and current. This decay mechanism is based on the formation of electron-irradiation-induced microscopic defects that act as recombination centers and reduce the lifetime of carriers.     

The effect of cathode materials on reactive ion etching of silicon and silicon dioxide in a CF4 plasma

Silicon and silicon dioxide have been Reactive Ion Etched in a CF₄ plasma using a diode sputtering configuration to achieve etching. Pressures ranged from 20 to 100 millitorr and power densities to the RF cathode were between 0.1 and 1.0 W/cm². The effect of cathode material on the quality of etched surfaces and on etch rates has been investigated. It has been observed that the etch rate of silicon decreases as the area of silicon exposed to the plasma is increased and that this silicon loading effect is strongly influenced by the material covering the balance of the cathode. For instance, the silicon loading effect is much more pronounced when silicon dioxide rather than aluminum is used to cover the balance of the cathode. This silicon loading effect was investigated further by varying RF power. It was found that loading a silicon dioxide covered cathode with silicon wafers decreases the dependence of silicon etch rate on power. The silicon dioxide etch rate and its dependence on RF power are the same whether silicon, silicon dioxide or aluminum is used to cover the balance of the cathode. Possible explanations for these experimental results will be discussed.     

Bulk passivation of multicrystalline silicon solar cells induced by high‐rate‐deposited (> 1 nm/s) silicon nitride films

Silicon nitride (a‐SiN_x:H) films deposited by the expanding thermal plasma at high rate (> 1 nm/s) have been studied for application as anti‐reflection coatings for multicrystalline silicon (mc‐Si) solar cells. Internal quantum efficiency measurements have revealed that bulk passivation is achieved after a firing‐through process of the a‐SiN_x:H as deposited from NH₃/SiH₄ and N₂/SiH₄ plasmas. However, the a‐SiN_x:H films deposited from N₂/SiH₄ show a lower passivation quality than those deposited from NH₃/SiH₄. This has been attributed to a poorer thermal stability of the films deposited from the N₂/SiH₄ plasma, resulting in structural changes within the film during the firing step. Copyright © 2002 John Wiley & Sons, Ltd.     

65nm n沟MOSFET的重离子辐照径迹效应研究

重离子在SiO2中能产生永久径迹,因此它可能对MOS器件电学特性产生影响。文章用Geant4软件对Au和Sn两种离子进行蒙特卡洛模拟,重点分析高能粒子在SiO2中的能量沉积及径迹。基于模拟分析,对专门设计的65 nm n沟MOSFET器件进行Sn离子辐照实验,发现辐照后Ids和Ig明显增大,分析器件辐照前后阈值电压、跨导、沟道电流以及栅漏电流等特性参数变化的原因。     

An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit

In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions; in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era.     

The influence of dose and protecting mask on electrically active defects induced by ion implantation in silicon

We present a study of electrically active defects induced by ion implantation, for two dopants: arsenic and phosphorous. Our analysis technique is Deep Level Transient Spectroscopy (D.L.T.S.). We have studied the generation of defects by direct implantation, and indirect implantation, that is through an SiO₂ layer. We follow the defect spectrum evolution for different doses (10⁸ to 10¹⁴ atoms/cm²) and for different annealing temperatures (from room temperature up to 800° C). The comparison of our results with other published ones allows us to improve the knowledge about the role of a protecting oxide layer, the influence of moderate thermal annealing, and the effect of oxygen on deep centers produced by ion bombardment.     

Damage and strain in pseudomorphic vs relaxed GexSi1−x layers on Si(100) generated by Si ion irradiation

We compare both the strain and damage that 100 keV Si irradiation at room temperature introduces in pseudomorphic and relaxed Ge_xSi_1−x films grown on Si(100) substrates. The ion range is such that the Si/Ge_xSi_1−x interface is not significantly damaged. The amount of damage produced in pseudomorphic and relaxed Ge_xSi_1−x layers of similar x for irradiation doses up to 2.5 × 10¹⁴ Si/cm² is the same, which proves that a pre-existing uniform strain does not noticeably affect the irradiation-induced damage. However, the irradiation-induced strain does depend on the pre-existing strain of the samples. Possible interpretations are discussed. On leave from Inst. voor Kern en Stralingsfysika, Catholic University of Leuven, Belgium.     

Industrial high‐rate (∼5 nm/s) deposited silicon nitride yielding high‐quality bulk and surface passivation under optimum anti‐reflection coating conditions

High‐quality surface and bulk passivation of crystalline silicon solar cells has been obtained under optimum anti‐reflection coating properties by silicon nitride (a‐SiN_x:H) deposited at very high deposition rates of ∼5 nm/s. These a‐SiN_x:H films were deposited using the expanding thermal plasma (ETP) technology under regular processing conditions in an inline industrial‐type reactor with a nominal throughput of 960 solar cells/hour. The low surface recombination velocities (50–70 cm/s) were obtained on p‐type silicon substrates (8·4 Ω cm resistivity) for as‐deposited and annealed films within the broad refractive index range of 1·9–2·4, which covers the optimum bulk passivation and anti‐reflection coating performance reached at a refractive index of ∼2·1. Copyright © 2005 John Wiley & Sons, Ltd.     

Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for crystalline silicon modules undergoing potential‐induced degradation stress testing

We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current–voltage (I–V) curve measured at the elevated stress temperature, during potential‐induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum‐power temperature translation methods found in the literature. For the first method, which is based on the maximum‐power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two‐diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large‐scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum‐power temperature translation method, by taking advantage of the near‐linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Copyright © 2015 John Wiley & Sons, Ltd.