Analytical modeling of high performance single-walled carbon nanotube field-effect-transistor

We present a novel analytical modeling of a zigzag single-walled semiconducting carbon nanotube field effect transistor (CNFET) by incorporating quasi-one-dimensional (Q1D) top-of-a-potential barrier approach. By implementing multimode carrier transport, we explore and compare the performance of a low- (360 cm²/Vs) and high-mobility (7200 cm²/Vs) CNFET model with experimental data from nanotube and 45 nm MOSFET, respectively, as well as existing compact models. Mobility and carrier concentration models are also developed to obtain a good matching with physical data. For a high mobility CNFET, we found that a maximum of 120 μA is obtained. In addition to this, a CNT-based inverter is also developed by constructing n-type and p-type CNFET in ORCAD’s analog behavioral model (ABM). A gain of as high as 5.2 is forecasted for an inverter of 80 nm CNFET.     

Feasibility and performance region modeling of analog and digital circuits

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.This research was supported in part by a grant from NSF (MIP-9110719)     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

新型高性能电工材料应用特性建模的模块化设计

传统的电工材料主要是指电工产品中常用的导体材料、半导体材料、磁性材料以及电工绝缘材料等,然而随着社会的进步和科技的发展,新型高性能的电工材料因其优异的性能,给电工行业注入了新鲜的血液。尤其是它在军民两用高科技领域中的应用,有着出色的表现,同时,也在越来越多的领域中有着广泛的应用背景。     

Poly(3,4-ethylenedioxythiophene)/graphene/carbon nanotube ternary composites with improved thermoelectric performance

Polymer based ternary thermoelectric composites have been studied. Here, poly(3,4-ethylenedioxythiophene)/graphene/carbon nanotube (PEDOT/graphene/CNT) ternary composites are prepared by in situ polymerization and subsequent physical mixing. Then, the morphology is directly observed by scanning electron microscopy. Finally, the thermoelectric performances are measured and discussed, where the effect of acid-treatment is investigated and comparison with those of the neat PEDOT and the binary PEDOT/graphene composite is conducted.     

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects

We introduce a Nyquist stability analysis of coupled mixed CNT bundle (MCB) for sub-threshold interconnects. In this analysis, the dependence of relative stability of sub-threshold MCBs with specific and probabilistic distribution of CNTs, on the geometry and probability of metallic CNTs, has been obtained. Using the proposed ABCD model and Nyquist stability criterion for sub-threshold MCBs, we show that, by increasing the diameter of each individual CNT and the length of MCB, the sub-threshold MCB interconnect system becomes more stable, while a densely packed MCB reduces the relative stability. Moreover, the crosstalk impact results in the greater stability of sub-threshold MCB system in comparison to a single interconnect. The crosstalk delay of MCB and composite Cu-MWCNT interconnects is also compared at various lengths. This is, so far, the first instance that such an analysis has been presented for coupled sub-threshold MCB interconnects.     

Thermal characteristics evaluation for board-level high performance flip-chip package equipped with vapor chamber as heat spreader

Thermal analysis was performed in this work to compare the thermal performance of a board-level high performance flip-chip ball grid array package equipped with solid Cu or vapor chamber (VC) as the heat spreader and Al-filler gel or In solder as the thermal interface material (TIM). The effect of different heat source sizes was also examined. Numerical results indicate that for the particular test vehicle under a power dissipation of 160 W, the thermal performance is remarkably enhanced by switching TIM from Al-filler gel to In solder while the enhancement by using VC instead of solid Cu heat spreader is only observable when In solder is incorporated. Moreover, the performance of VC gradually enhances then retards as the heat source size decreases. The retardation can be attributed to the more dominant role of die in heat dissipation when the heat source size gradually shrinks.     

器件参数宏模型的精确建立及其在模拟集成电路性能建模与优化中的应用

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presnted to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs.The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.     

Formal modeling and quantitative evaluation for information system survivability based on PEPA

Survivability should be considered beyond security for information system. To assess system survivability accurately, for improvement, a formal modeling and analysis method based on stochastic process algebra is proposed in this article. By abstracting the interactive behaviors between intruders and information system, a transferring graph of system state oriented survivability is constructed. On that basis, parameters are defined and system behaviors are characterized precisely with performance evaluation process algebra （PEPA）, simultaneously considering the influence of different attack modes. Ultimately the formal model for survivability is established and quantitative analysis results are obtained by PEPA Workbench tool. Simulation experiments show the effectiveness and feasibility of the developed method, and it can help to direct the designation of survivable system.     

Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach

There is a need to explore circuit designs in new emerging technologies for their rapid commercialization to extend Moore’s law beyond 22 nm technology node. Carbon nanotube based transistor (CNFET) has significant potential to replace CMOS in the future due to its better electrostatics and higher mobility. This paper presents a complete optimal design of an inverting amplifier in CMOS, CNFET and hybrid technologies. We investigate and conceptually explain the performance measure of the amplifier at 32 nm technology node in terms of operating voltage, number of carbon nanotubes (CNT), diameter and pitch (inter-nanotube distance) variations of carbon nanotubes in a CNFET transistor in pure and hybrid technologies for area, power and performance optimization. This paper also explores the scope, possibilities and challenges associated with pure CNFET and hybrid amplifiers. We have found that pure CNFET amplifier provided good amplification while hybrid pCNFET-nMOS amplifier offered excellent frequency response and pMOS-nCNFET amplifier gave better transient performance compared with planar CMOS.     

WCDMA随机接入信道的数学建模及性能分析

文章主要讨论了宽带码分多址(WCDMA)网络中无线小区随机接入信道(RACH)的数学建模方法及性能分析.首先介绍了WCDMA的RACH及信息发送方式,然后描述了RACH随机接入过程的时隙ALOHA接入方式,并在此基础上重点分析了RACH数学建模的方法和详细过程,给出了RACH吞吐量的计算公式,最后,对RACH的性能进行了分析.     

Electrical performance of the embedded-type surface electrodes containing carbon and silver nanowires as fillers and one-step organosoluble polyimide as a matrix

Embedded-type surface electrodes with silver nanowire (AgNW) and carbon nanotube (CNT) as conductive fillers and organosoluble polyimide (PI) as a matrix were investigated for their electrical conductivity and electrical durability under cyclic bending. The chosen polyimide was constituted with 4,4′-oxydiphthalic dianhydride and 2,2-bis(3-amino-4-hydroxyphenyl)hexafluoropropane through a one-step process. Two types of surface electrodes of CNT/PI and AgNW/PI were prepared at 90 °C. The flexible CNT/PI and AgNW/PI surface electrodes not only had high electrical conductivities of 6.3 and 100 S/cm, respectively, after 30 spraying cycles but also kept electrical durability after 1200-time bending tests. The ITO-coated ITO/PI and ITO/AgNW/PI electrodes, for a comparative purpose, had severe electrical failure under cyclic bending.     

Fabrication of carbon nanotube arrays for field emission and sensor devices by nanoimprint lithography

This work brings forth the idea of incorporating insulation in the resist used for ultraviolet (UV) curing nanoimprint lithography (NIL). Carbon nanotubes (CNTs) are grown in the space between two insulated resist patterns on the conductive substrate to make CNTs arrays. Two imprinting processes, soft UV curing NIL with DRPPR process and novel NIL without cured residual resist, are presented to achieve the insulation patterns. First the fabricating process is performed using a polydimethylsiloxane (PDMS) stamp. Subsequently, inductively coupled plasma (ICP) is essential to wipe off the residual resist film. To avoid the ICP process, a novel UV curing NIL is presented. Its special hard quartz stamp with chrome shelter can protect the residual resist film out of curing during the UV exposure process, and the uncured resist can be easily removed by ultrasonic vibration in organic solutions. The CNT arrays are prepared on the patterned substrates by the pyrolysis of iron phthalocyanine (FePc). Field emission experiments reveal that the turn-on field of those CNTs arrays is low to 1.3 V/um.     

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.     

5G信道建模与性能测试方法

随着5G移动通信系统的快速发展,5G基站和终端在实际外场环境下的吞吐量性能对用户体验至关重要。如何在室内精确建模和复现外场信道环境,成为学术界和产业界的研究热点。介绍了4G和5G的信道建模方法,并针对5G终端设备,阐述了目前实验室多输入多输出(multi-input multi-output,MIMO)空口(overthe-air,OTA)测试解决方案的优势,然后给出了具体的OTA信道建模原理描述以及吞吐量仿真结果,以期为相关工作提供参考。     

不同板材密集散热孔耐热性能对比与分析

随着线路板不断向高密度化方向发展,客户设计散热过孔的孔壁间距也随之减少,密集散热孔在热应力测试后出现分层的风险也相应加大。为了降低此类风险,我们测试并分析了不同板材、不同孔壁间距对分层的影响,为生产和设计提供了有价值的参考。     

Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV

Through-silicon vias (TSVs) have provided an attractive solution for three-dimensional (3D) integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output (I/O) density and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via (vertical interconnect access) line of a driver-TSV-load (DTL) system. The via radius and height are used to estimate the bundle aspect ratio (AR) and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 : 1 in comparison to AR = 6 : 1.     

高效液相色谱法测定头孢噻吩钠含量和有关物质

建立高效液相色谱法（HPLC）测定头孢噻吩钠含量和有关物质。色谱条件以C18为固定相,色谱柱：（4.6mm×250mm,5μm）;流动相为0.207mol/L醋酸钠溶液（用冰醋酸调pH值至5.9）-乙醇-乙腈（82：2：16）,流速为：1.0mL/min;检测波长：254nm：柱温;40℃。结果：头孢噻吩钠含量在55.8μg/mL至464.4μg/mL呈良好线性关系,r=0.9999：平均回收率100.2%;最低检测限为3ng（1ng/μL×3μL）。本法简单、准确,重现性、分离效果好,能较好的进行孢噻吩钠含量和有关物质测定。