Properties of thick SiO2/Si structure formed at 120 °C by use of two-step nitric acid oxidation method

Thick (i.e., ∼10 nm) SiO₂/Si structure has been formed at 121 °C by immersion of Si in relatively low concentration HNO₃ followed by that in 68 wt.% HNO₃ (i.e., two-step nitric acid (HNO₃) oxidation method of Si, NAOS) and spectroscopic properties and electrical characteristics of the NAOS SiO₂ layers are investigated. The SiO₂ thickness strongly depends on the concentration of HNO₃ aqueous solutions employed in the initial oxidation, and it becomes the largest at the HNO₃ concentration of 40 wt.%. The MOS diodes with the ∼9 nm SiO₂ layer formed by the NAOS method possess a relatively low leakage current density (e.g., 10⁻⁸ A/cm² at the forward bias of 1 V) and it is further decreased by more than one order of magnitude by post-metallization annealing (PMA) in hydrogen at 250 °C. The good leakage characteristic is attributable to atomically flat SiO₂/Si interfaces and high atomic density of 2.30-2.32 × 10²² atoms/cm³ of the NAOS SiO₂ layers. High-density interface states are present in as-prepared SiO₂ layers and they are eliminated by PMA in hydrogen.     

Low temperature fabrication of 5-10 nm SiO2/Si structure using advanced nitric acid oxidation of silicon (NAOS) method

We have developed the advanced nitric acid oxidation of Si (NAOS) method to form relatively thick (5-10 nm) SiO₂/Si structure with good electrical characteristics. This method simply involves immersion of Si in 68 wt% nitric acid aqueous solutions at 120 °C with polysilazane films. Fourier transform infrared absorption (FT-IR) measurements show that the atomic density of the NAOS SiO₂ layer is considerably high even without post-oxidation anneal (POA), i.e., 2.28 × 10²² atoms/cm², and it increases by POA at 400 °C in wet-oxygen (2.32 × 10²² atoms/cm²) or dry-oxygen (2.30 × 10²² atoms/cm²). The leakage current density is considerably low (e.g., 10⁻⁵ A/cm² at 8 MV/cm) and it is greatly decreased (10⁻⁸ A/cm² at 8 MV/cm) by POA at 400 °C in wet-oxygen. POA in wet-oxygen increases the atomic density of the SiO₂ layer, and decreases the density of oxide fixed positive charges.     

Formation of atomically smooth SiO2/SiC interfaces at ∼120 °C by use of nitric acid oxidation method

Conventional thermal oxidation of SiC requires heating at ∼1100 °C. In the present study, we have developed a method of oxidizing SiC at low temperatures (i.e., ∼120 °C) to form relatively thick silicon dioxide (SiO₂) layers by use of nitric acid. When 4H-SiC(0 0 0 1) wafers are immersed in 40 wt% HNO₃ at the boiling temperature of 108 °C and the boiling is kept for 5 h after reaching the azeotropic point (i.e., 68 wt% HNO₃ at 121 °C), 8.1 nm thick SiO₂ layers are formed on the SiC substrates. High resolution transmission electron microscopy measurements show that the SiO₂/SiC interface is atomically flat and the SiO₂ layer is uniform without bunching. When SiC is immersed in an azeotropic mixture of HNO₃ with water from the first, the SiO₂ thickness is less than 0.3 nm. The metal-oxide-semiconductor (MOS) diodes with the SiO₂ layer formed by the nitric acid oxidation method possess a considerably low leakage current density.     

Band alignment of SiO2/Si structure formed with nitric acid vapor below 500 °C

A relatively thick (i.e., ∼9 nm) SiO₂ layer can be formed by oxidation of Si with nitric acid (HNO₃) vapor below 500 °C. In spite of the low temperature formation, the leakage current density flowing through the SiO₂ layer is considerably low, and it follows the Fowler-Nordheim mechanism. From the Fowler-Nordheim plots, the conduction band offset energy at the SiO₂/Si interface is determined to be 2.57 and 2.21 eV for HNO₃ vapor oxidation at 500 and 350 °C, respectively. From X-ray photoelectron spectroscopy measurements, the valence band offset energy is estimated to be 4.80 and 4.48 eV, respectively, for 500 and 350 °C oxidation. The band-gap energy of the SiO₂ layer formed at 500 °C (8.39 eV) is 0.68 eV larger than that formed at 350 °C. The higher band-gap energy for 500 °C oxidation is mainly attributable to the higher atomic density of the SiO₂ layer of 2.46 × 10²²/cm³. Another reason may be the absence of SiO₂ trap-states.     

Formation of 10-30 nm SiO2/Si structure with a uniform thickness at ∼120 °C by nitric acid oxidation method

Silicon dioxide (SiO₂) layers with a thickness more than 10 nm can be formed at ∼120 °C by direct Si oxidation with nitric acid (HNO₃). Si is initially immersed in 40 wt.% HNO₃ at the boiling temperature of 108 °C, which forms a ∼1 nm SiO₂ layer, and the immersion is continued after reaching the azeotropic point (i.e., 68 wt.% HNO₃ at 121 °C), resulting in an increase in the SiO₂ thickness. The nitric acid oxidation rates are the same for (1 1 1) and (1 0 0) orientations, and n-type and p-type Si wafers. The oxidation rate is constant at least up to 15 nm SiO₂ thickness (i.e., 1.5 nm/h for single crystalline Si and 3.4 nm/h for polycrystalline Si (poly-Si)), indicating that the interfacial reaction is the rate-determining step. SiO₂ layers with a uniform thickness are formed even on a rough surface of poly-Si thin film.     

Nitric acid oxidation method to form SiO2/3C-SiC structure at 120 °C

3C-SiC(0 0 1) surfaces are considerably rough with the roughness root mean square value (R_ms) of 1.3 nm, but the surfaces become considerably smooth (i.e., R_ms of 0.5 nm) by heat treatment in pure hydrogen at 400 °C. Two-step nitric acid (HNO₃) oxidation (i.e., immersion in ∼40 wt% HNO₃ followed by that in 68 wt% HNO₃) performed after the hydrogen treatment can oxidize 3C-SiC at extremely low temperature of ∼120 °C, forming thick SiO₂ (e.g., 21 nm) layers. With no hydrogen treatment, the leakage current density of the 〈Al/SiO₂/3C-SiC〉 metal-oxide-semiconductor (MOS) diodes is high, while that for the MOS diodes with the hydrogen treatment is considerably low (e.g., ∼10⁻⁶ A/cm² at the forward gate bias of 1 V) due to the formation of uniform thickness SiO₂ layers. The MOS diodes with the hydrogen treatment show capacitance-voltage curves with accumulation, depletion, and deep-depletion characteristics.     

Reduced dielectric loss and leakage current in CaCu3Ti4O12/SiO2/CaCu3Ti4O12 multilayered films

The CaCu₃Ti₄O₁₂/SiO₂/CaCu₃Ti₄O₁₂ (CCTO/SiO₂/CCTO) multilayered films were prepared on Pt/Ti/SiO₂/Si substrates by pulsed laser deposition method. It has been demonstrated that the dielectric loss and the leakage current density were significantly reduced with the increase of the SiO₂ layer thickness, accompanied with a decrease of the dielectric constant. The CCTO film with a 20 nm SiO₂ layer showed a dielectric loss of 0.065 at 100 kHz and the leakage current density of 6×10⁻⁷ A/cm² at 100 kV/cm, which were much lower than those of the single layer CCTO films. The improvement of the electric properties is ascribed to two reasons: one is the improved crystallinity; the other is the reduced free carriers in the multilayered films.     

Photoluminescence of Si from Si nanocrystal-doped SiO2/Si multilayered sample

A multilayered Si nanocrystal-doped SiO₂/Si (or Si-nc:SiO₂/Si) sample structure is studied to acquire strong photoluminescence (PL) emission of Si via modulating excess Si concentration. The Si-nc:SiO₂ results from SiO thin film after thermal annealing. The total thickness of SiO layer remains 150 nm, and is partitioned equally into a number of sublayers (N = 3, 5, 10, or 30) by Si interlayers. For each N-layered sample, a maximal PL intensity of Si can be obtained via optimizing the thickness of Si interlayer (or d_Si). This maximal PL intensity varies with N, but the ratio of Si to O is nearly a constant. The brightest sample is found to be that of N = 10 and d_Si = 1 nm, whose PL intensity is ∼5 times that of N = 1 without additional Si doping, and ∼2.5 times that of Si-nc:SiO₂ prepared by co-evaporating of SiO and Si at the same optimized ratio of Si to O. Discussions are made based on PL, TEM, EDX and reflectance measurements.     

SiC/SiO2 coating for improving the oxidation resistive property of carbon nanofiber

The SiC/SiO₂ deposition was performed to improve the oxidation resistive properties of carbon nanofiber (CNF) from electrospinning at elevated temperatures through sol-gel process. The stabilized polyacrylonitrile (PAN) fibers were coated with SiO₂ followed by heat treatment up to 1000 and 1400 °C in an inert argon atmosphere. The chemical compositions of the CNFs surface heat-treated were characterized as C, Si and O existing as SiC and SiO₂ compounds on the surface. The uniform and continuous coating improved the oxidation resistance of the carbon nanofibers. The residual weight of the composite was 70-80% and mixture of SiC, SiO₂ and some residual carbon after exposure to air at 1000 °C.     

Microstructure and dielectric properties of La2O3 doped amorphous SiO2 films as gate dielectric material

As a potential gate dielectric material, the La₂O₃ doped SiO₂ (LSO, the mole ratio is about 1:5) films were fabricated on n-Si (0 0 1) substrates by using pulsed laser deposition technique. By virtue of several measurements, the microstructure and electrical properties of the LSO films were characterized. The LSO films keep the amorphous state up to a high annealing temperature of 800 °C. From HRTEM and XPS results, these La atoms of the LSO films do not react with silicon substrate to form any La-compound at interfacial layer. However, these O atoms of the LSO films diffuse from the film toward the silicon substrate so as to form a SiO₂ interfacial layer. The thickness of SiO₂ layer is only about two atomic layers. A possible explanation for interfacial reaction has been proposed. The scanning electron microscope image shows the surface of the amorphous LSO film very flat. The LSO film shows a dielectric constant of 12.8 at 1 MHz. For the LSO film with thickness of 3 nm, a small equivalent oxide thickness of 1.2 nm is obtained. The leakage current density of the LSO film is 1.54 × 10⁻⁴ A/cm² at a gate bias voltage of 1 V.     

Nitric acid method for fabrication of gate oxides in TFT

We have developed low temperature formation methods of SiO₂ layers which are applicable to gate oxide layers in thin film transistors (TFT) by use of nitric acid (HNO₃). Thick (>10 nm) SiO₂ layers with good thickness uniformity (i.e., ±4%) can be formed on 32 cm × 40 cm substrates by the two-step nitric acid oxidation method in which initial and subsequent oxidation is performed using 40 and 68 wt% (azeotropic mixture) HNO₃ aqueous solutions, respectively. The nitric acid oxidation of polycrystalline Si (poly-Si) thin films greatly decreases the height of ridge structure present on the poly-Si surfaces. When poly-Si thin films on 32 cm × 40 cm glass substrates are oxidized at azeotropic point (i.e., 68 wt% HNO₃ aqueous solutions at 121 °C), ultrathin (i.e., 1.1 nm) SiO₂ layers with a good thickness uniformity (±0.05 nm) are formed on the poly-Si surfaces. When SiO₂/Si structure fabricated using plasma-enhanced chemical vapor deposition is immersed in 68 wt% HNO₃, oxide fixed charge density is greatly decreased, and interface states are eliminated. The fixed charge density is further decreased by heat treatments at 200 °C, and consequently, capacitance-voltage characteristics which are as good as those of thermal SiO₂/Si structure are achieved.     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

High temperature characteristics of ZnO-based MOS-FETs with a photochemical vapor deposition SiO2 gate dielectric

The authors report the fabrication of ZnO-based metal-oxide-semiconductor field effect transistors (MOSFETs) with a high quality SiO₂ gate dielectric by photochemical vapor deposition (photo-CVD) on a sapphire substrate. Compared with ZnO-based metal-semiconductor FETs (MESFETs), it was found that the gate leakage current was decreased to more than two orders of magnitude by inserting the photo-CVD SiO₂ gate dielectric between ZnO and gate metal. Besides, it was also found that the fabricated ZnO MOSFETs can achieve normal operation of FET, even operated at 150 °C. This could be attributed to the high quality of photo-CVD SiO₂ layer. With a 2 μm gate length, the saturated I_ds and maximum transconductance (G_m) were 61.1 mA/mm and 10.2 mS/mm for ZnO-based MOSFETs measured at room temperature, while 45.7 mA/mm and 7.67 mS/mm for that measured at 150 °C, respectively.     

Luminescence properties of Ge implanted SiO2:Ge and GeO2:Ge films

We have investigated cathodeluminescence (CL) of Ge implanted SiO₂:Ge and GeO₂:Ge films. The GeO₂ films were grown by oxidation of Ge substrate at 550 °C for 3 h in O₂ gas flow. The GeO₂ films on Ge substrate and SiO₂ films on Si substrate were implanted with Ge-negative ions. The implanted Ge atom concentrations in the films were ranging from 0.1 to 6.0 at%. To produce Ge nanoparticles the SiO₂:Ge films were thermally annealed at various temperatures of 600-900 °C for 1 h in N₂ gas flow. An XPS analysis has shown that the implanted Ge atoms were partly oxidized. CL was observed at wavelengths around 400 nm from the GeO₂ films before and after Ge⁻-implantation as well as from SiO₂:Ge films. After Ge⁻-implantation of about 0.5 at% the CL intensity has increased by about four times. However, the CL intensity from the GeO₂:Ge films was several orders of magnitude smaller than the intensity from the 800 °C-annealed SiO₂:Ge films with 0.5 at% of Ge atomic concentration. These results suggested that the luminescence was generated due to oxidation of Ge nanoparticles in the SiO₂:Ge films.     

Reaction products and oxide thickness formed by Ti out-diffusion and oxidization in poly-Pt/Ti/SiO2/Si with oxide films deposited

In the paper, we present experimental results to enhance the understanding of Ti out-diffusion and oxidization in commercial poly-Pt/Ti/SiO₂/Si wafers with perovskite oxide films deposited when heat-treated in flowing oxygen ambient. It indicates that when heat-treated at 550 and 600 °C, PtTi₃+PtTi and PtTi are the reaction products from interfacial interaction, respectively; while heat-treated at 650 °C and above, the products become three layers of titanium oxides instead of the alloys. Confirmed to be rutile TiO₂, the first two layers spaced by 65 nm encapsulate the Pt surface by the first layer with 60 nm thick forming at its surface and by the next layer with 35 nm thick inserting its original layer. In addition, the next layer is formed as a barrier to block up continuous diffusion paths of Ti, and thus results in the last layer of TiO_2−x formed by the residual Ti oxidizing.     

Pulsed plasma ion source to create Si nanocrystals in SiO2 substrates

A pulsed KrF excimer laser of irradiance of about 10⁸ W/cm² was utilized to synthesize Si nanocrystals on SiO₂/Si substrates. The results were compared with that ones obtained by applying low bias voltage to Si(1 0 0) target in order to control the kinetic energy of plasma ions. Glancing incidence X-ray diffraction spectra indicate the presence of silicon crystalline phases, i.e. (1 1 1) and (2 2 0), on SiO₂/Si substrates. The average Si nanocrystal size was estimated to be about 45 nm by using the Debye-Scherrer formula. Scanning electron microscopy and atomic force microscopy images showed the presence of nanoparticles of different size and shape. Their distribution exhibits a maximum concentration at 49 nm and a fraction of 14% at 15 nm.     

Annealing temperature dependence of Raman scattering in Si/SiO2 superlattice prepared by magnetron sputtering

Si/SiO₂ superlattices were prepared by magnetron sputtering, and the deposition temperature and annealing temperature had a great influence on the superlattice structure. In terms of SEM images, the mean size of Si nanocrystals annealed at 1100 °C is larger than that of nanocrystals annealed at 850 °C. It was found that the films deposited at room temperature are amorphous. With increasing deposition temperature, the amorphous and crystalline phases coexist. With increasing annealing temperature, the Raman intensity of the peak near 470 cm⁻¹ decreases, and the intensity of that at 520 cm⁻¹ increases. Also, on increasing the annealing temperature, the Raman peak near 520 cm⁻¹ shifts and narrows, and asymmetry emerges. A spherical cluster is used to model the nanocrystals in Si/SiO₂ superlattices, and the observed Raman spectra are analyzed by combining the effects of confinement on the phonon frequencies. Raman spectra from a variety of nanocrystalline silicon structures were successfully explained in terms of the phonon confinement effect. The fitted results agreed well with the experimental observations from SEM images.     

An XPS study and electrical properties of Pb1.1Zr0.53Ti0.47O3/PbO/Si (MFIS) structures according to the substrate temperature of the PbO buffer layer

PbO and PZT thin films were deposited on the p-type (1 0 0) Si substrate by the rf magnetron sputtering method with PbO and Pb_1.1Zr_0.53Ti_0.47O₃ targets for the application of the metal-ferroelectric-insulator-semiconductor (MFIS) structure. The MFIS structures with the PbO buffer layer show the good electric properties including a high memory window and a low leakage current density. The maximum value of the memory window is 2.0 V under the applied voltage of 9 V for the Pt/PZT (200 nm, 400 °C)/PbO (80 nm)/Si structures with the PbO buffer layer deposited at the substrate temperature of 300 °C. From the X-ray photoelectron spectroscopy (XPS) results, we could confirm that the substrate temperature of PbO affects the chemical states of the interface between the PbO buffer layer and Si substrate, which results in the inter-diffusion of Pb and the formation of the intermediate phases (PbSiO₃). And the existence of the undesired SiO₂ layer, which is the low dielectric layer, was confirmed at the surface region of the Si substrate by the XPS depth profile analysis.     

On the influence of the surface roughness onto the ultrathin SiO2/Si structure properties

The surface roughness of the semiconductor substrate substantially influences properties of the whole semiconductor/oxide structure. SiO₂/Si structures were prepared by using low temperature nitric acid oxidation of silicon (NAOS) method and then the whole structure was passivated by the cyanidization procedure. The influence of the surface morphology of the silicon substrate onto the electrical properties of ultrathin NAOS SiO₂ layer was investigated. Surface height function properties were studied by the AFM method and electrical properties were studied by the STM method. The complexity of analyzed surface structure was sensitive to the oxidation and passivation steps. For describing changes in the oxide layer structure, several fractal measures in an analysis of the STM images were used. This fractal geometry approach enables quantifying the fine spatial changes in the tunneling current spectra.     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.