陷阱效应对4H-SiC MESFET频率特性的影响

 针对4H-SiC 射频MESFET中的陷阱效应,建立了基于解析模型的器件小信号参数模型,引入能够反映陷阱影响的参数R_ds ″ 、g_m ″ 、C_ss等,从而能够由此分析器件特性随频率偏移的情况.对沟道缓冲层界面深能级陷阱的分析表明,4H-SiC MESFET的跨导既有正向偏移,也有负向偏移.偏移频率在室温下不足1Hz,但在600K的温度下则可达到MHz的量级.结合自热效应模型,论文还分析了栅、漏极偏置和温度对器件频率偏移特性的影响.模拟结果表明,随着温度的上升,偏移频段上升.本文的模拟分析对器件的设计提供了理论上的依据.     

陷阱效应对4H-SiC MESFET温度特性的影响

针对4H-SiC射频MESFET中的自热效应,建立了基于解析模型的材料参数温度模型和器件直流模型.研究了由陷阱造成的背栅效应,并结合材料的温度特性分析了温度升高对器件特性的影响.分析了陷阱对器件特性的影响,并进一步阐明了陷落-发射机制.计算得到陷阱能级为1.07eV,俘获截面为1×10-8cm2,器件的自升温达到100K以上,能够较好地反映实验结果.分析结果表明,背栅电势随陷阱浓度的增大而增大,并随着漏极电压的增大而减小,在室温下达到～3V.另外,由于器件中存在自热效应,背栅电势随漏压的变化加剧.这些模拟分析对实际器件的设计及工艺制造提供了理论上的依据.     

陷阱效应对4H-SiC MESFET温度特性的影响

针对4H-SiC射频MESFET中的自热效应,建立了基于解析模型的材料参数温度模型和器件直流模型.研究了由陷阱造成的背栅效应,并结合材料的温度特性分析了温度升高对器件特性的影响.分析了陷阱对器件特性的影响,并进一步阐明了陷落-发射机制.计算得到陷阱能级为1.07eV,俘获截面为1×10-8cm2,器件的自升温达到100K以上,能够较好地反映实验结果.分析结果表明,背栅电势随陷阱浓度的增大而增大,并随着漏极电压的增大而减小,在室温下达到～3V.另外,由于器件中存在自热效应,背栅电势随漏压的变化加剧.这些模拟分析对实际器件的设计及工艺制造提供了理论上的依据.     

4H-SiC MESFET与SBD中子辐照效应的研究

本文研究了4H-SiC MESFET与Ni,Ti/4H-SiC SBD的中子辐照效应,中子归一化能量为1MeV,最高中子注量和gamma射线累积总剂量分别为1×1015n/cm2和3.3Mrad(Si)。经过1×1013n/cm2的辐照剂量后, SiC MESFET的电学特性仅有轻微的变化,Ni、Ti/4H-SiC以及SiC MESFET栅极肖特基接触的 都没有明显变化;随着辐照中子注量的进一步上升,SiC MESFET的漏极电流下降,夹断电压上升。辐照剂量达到1×1014n/cm2,夹断电压从辐照前的-12.5V上升为约-11.5V。当中子辐照注量达到2.5×1014n/cm2时,SiC MESFET栅极肖特基接触的 比辐照前有一定的下降。分析认为SiC MESFET和SBD的退化主要是由中子辐照引入的体材料损伤造成的。本文的研究表明,提高器件有源区的掺杂浓度可以提高中子辐照容限。     

一种用于非线性分析的新型4H-SiC MESFET大信号经验模型

提出了一种简洁的新型4H-SiCMESFET经验大信号模型.在Materka漏电流模型基础上,改进了沟道调制因子和饱和电压系数的建模方式,电容模型采用了改进的电荷守恒模型.参数的提取和优化采用了Levenberg-Marquardt优化方法.在偏置点VDS=20V,IDS=80mA和工作频率1.8GHz下,模型直流电流-电压扫描曲线、输出功率、功率附加效率和增益的模拟结果与实验数据符合良好.     

一种用于非线性分析的新型4H-SiC MESFET大信号经验模型

提出了一种简洁的新型4H-SiCMESFET经验大信号模型.在Materka漏电流模型基础上,改进了沟道调制因子和饱和电压系数的建模方式,电容模型采用了改进的电荷守恒模型.参数的提取和优化采用了Levenberg-Marquardt优化方法.在偏置点VDS=20V,IDS=80mA和工作频率1.8GHz下,模型直流电流-电压扫描曲线、输出功率、功率附加效率和增益的模拟结果与实验数据符合良好.     

基于实验与物理分析的4H-SiC射频功率MESFET大信号非线性精确电容模型

采用电荷控制理论和载流子速度饱和理论的物理分析方法,并结合Statz、Angelov等经验模型的描述方法,提出了常温下针对4H-SiC射频功率MESFET的大信号非线性电容模型.此模型在低漏源偏压区对栅源电容Cgs强非线性的描述优于Statz、Angelov等经验模型,计算量也远低于基于器件物理特性的数值模型,因而适合于大信号的电路设计与优化.     

基于实验与物理分析的4H-SiC射频功率MESFET大信号非线性精确电容模型

采用电荷控制理论和载流子速度饱和理论的物理分析方法,并结合Statz、Angelov等经验模型的描述方法,提出了常温下针对4H-SiC射频功率MESFET的大信号非线性电容模型.此模型在低漏源偏压区对栅源电容Cgs强非线性的描述优于Statz、Angelov等经验模型,计算量也远低于基于器件物理特性的数值模型,因而适合于大信号的电路设计与优化.     

Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression.Characteristics of the device have been investigated based on physical models for material properties and improved trap models.By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate （BG-FP） structure,it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance(C_gd) under a large drain voltage.A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_gd than a conventional FP.For microwave applications,4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel.For high power applications,the proposed structure is able to endure higher operating voltage as well.The maximum saturation current density of 460 mA/mm is yielded.Also,the gate-lag ratio under a drain voltage of 20 V is close to 90%.In addition,5%and 17.8%improvements in f_T and f_max are obtained compared with a BG-FP MESFET in AC simulation,respectively.Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.     

4H-SiC MESFET新结构的特性研究

提出了一种具有阶梯沟道和浮空金属板的新型4H-SiC MESFET结构。在双凹型4H-SiC MESFET的栅漏之间加入浮空金属板,并引入阶梯沟道,减少了靠近漏端的栅边缘的电场积聚,提高了击穿电压。对提出的结构进行二维数值模拟,结果表明,该结构的击穿电压达到232 V,相对于双凹型4H-SiC MESFET的击穿电压103 V,提高了125%,其饱和漏电流相对提高了4.1%,截止频率为15.1 GHz,最大振荡频率为69.2 GHz。该结构在击穿电压提高125%时,没有严重降低截止频率。     

n沟道4H-SiC MESFET研究

报告了4H-SiCMESFET的研制。通过对SiC关键工艺技术进行研究,设计出初步可行的工艺流程,并且制成单栅宽120μmn沟道4H-SiCMESFET,其主要直流特性为在Vds=30V时,最大漏电流密度Idss为56mA/mm,最大跨导Gm为15mS/mm;漏源击穿电压最高达150V;微波特性测试结果在fo=1GHz、Vds=32V时该器件最大输出功率7.05mW,在fo=1.8GHz、Vds=32V时最大输出功率3.1mW。     

基于陷阱的4H-SiC MESFET频散效应分析

在建立正确模型的基础上,运用ISE软件的二维仿真,模拟了4H-SiC MESFET在交流小信号条件下,表面陷阱和体陷阱对跨导和漏电导随频率变化的影响。分析了产生频散效应的原因以及内部机理,同时考虑了不同环境温度对跨导的频散影响。结果表明,在低频条件下,陷阱会导致跨导和漏电导频散,漏电压越大,环境温度越高,频散越不明显。     

4H-SiC MESFET直流I-V特性解析模型

提出一种改进的4H-SiC MESFET非线性直流解析模型,该模型基于栅下电荷的二维分布进行分析,在分析电场相关迁移率、速度饱和的基础上,考虑沟道长度调制效应对饱和区漏电流的影响,建立基于物理的沟道长度调制效应模型,模拟结果与实测的I-V特性较为吻合。在器件设计初期,可以有效地预测器件的工作状态。     

A novel 4H-SiC MESFET with a L-gate and a partial p-type spacer

A 4H-SiC MESFET incorporated with L-gate and partial p-type spacer (LP-MESFET) is proposed and simulated. The simulations show that obvious improvements can be obtained for the LP-MESFET compared to the conventional structure (C-MESFET), such as a 17% larger of the saturation current, a 36% higher of the breakdown voltage V_b and a 95% larger of the maximum output power densities. Furthermore, the decrease of the gate-drain capacitance (C_GD) will lead to an improved RF performance for the LP-MESFET.     

具有高掺杂表面层和阶梯栅结构SiC MESFETs双沟道器件研究

An improved dual-channel 4H-SiC MESFET with high doped n-type surface layer and step-gate structure is proposed, and the static and dynamic electrical performances are analyzed.A high doped n-type surface layer is applied to obtain a low source parasitic series resistance, while the step-gate structure is utilized to reduce the gate capacitance by the elimination of the depletion layer extension near the gate edge, thereby improving the RF characteristics and still maintaining a high breakdown voltage and a large drain current in comparison with the published SiC MESFETs with a dual-channel layer.Detailed numerical simulations demonstrate that the gate-to-drain capacitance, the gate-to-source capacitance, and the source parasitic series resistance of the proposed structure are about 4%, 7%, and 18% smaller than those of the dual-channel structure, which is responsible for 1.4 and 6 GHz improvements in the cut-off frequency and the maximum oscillation frequency.     

Improved dual-channel 4H-SiC MESFETs with high doped n-type surface layers and step-gate structure

the proposed structure are about 4%, 7%, and 18% smaller than those of the dual-channel structure, which is responsible for 1.4 and 6 GHz improvements in the cut-off frequency and the maximum oscillation frequency.     

4H-SiC MESFET结构与直流特性研究

运用二维器件模拟器ISETCAD对4H-SiCMESFET不同结构的直流特性进行了模拟,重点考虑表面陷阱对直流特性的影响。与凹栅结构相比,埋栅结构的器件降低了表面陷阱对电流的影响,饱和漏电流提高了37%,而且阈值电压的绝对值增大、跨导升高,对提高4H-SiCMES-FET器件的输出功率起到一定的作用。     

漂移层经碳处理后的4H-SiC PiN 二极管的特性与分析

The characteristics of 4H-SiC PiN diodes with a carbon-implanted drift layer was investigated and the reason of characteristics improvement was analyzed. The forward voltage drops of the diodes with carbonimplanted drift layer were around 3.3 V, which is lower than that of devices without carbon implantation, the specific-on resistance was decreased from 9.35 to 4.38 mΩcm² at 100 A/cm², and the reverse leakage current was also decreased. The influence of carbon incorporation in the Si C crystalline grids was studied by using deep-level transient spectroscopy（DLTS）. The DLTS spectra revealed that the Z_1/2 traps, which were regarded as the main lifetime limiting defects, were dramatically reduced. It is proposed that the reduction of Z_1/2 traps can achieve longer carrier lifetime in the drift layer, which is beneficial to the performance of bipolar devices.