一种开关电流电路时钟馈通的补偿技术

提出一种开关电流电路时钟馈通的补偿技术.这种技术可以同时取消误差电流中的常数项和信号关联项.在相同工艺条件下的HSPICE仿真结果表明:文中提出的时钟馈通补偿技术的开关电流存储单元与基本的开关电流存储单元相比,误差电流减小了10 0倍.     

开关电流电路中的时钟馈入效应

本文采用ＭＯＳ开关的集总时变ＲＣ模型，对开关电流（ＳＩ）电路中的时钟馈入效应进行了详细的理论分析，导出了开关电流镜中钟馈电压和钟馈电流的表达式，从而揭示出了钟馈电压／电流与工艺参数、ＭＯＳ器件尺寸、时钟信号幅值及其下降沿斜率等之间的内在关系。用它可对ＳＩ电路中时钟馈入的影响进行快速预测。文中的理论分析与ＳＰＩＣＥ仿真结果相一致。所提供的结果对于设计高精度低功耗ＳＩ电路有应用价值。     

开关电流电路及其误差分析

开关电流(SI)技术是有望取代开关电容技术的一种新的采样数据技术。首先介绍了开关电流技术的概念及优点,然后以SI电路基本存储单元为例分析了开关电流电路中可能存在的误差。最后,针对电路中存在的失配误差、传输误差、噪声误差及电荷注入误差等提出了一些解决方法,如S2I技术等。     

实现Folded-Cascode放大器快速建立的时钟馈通频率补偿

基于有源开关电容网络二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种用于Folded-Cascode放大器的频率补偿新方法,即通过MOS电容引入时钟馈通以调整电路阻尼因子η,使其达到MST状态,从而实现快速建立.研究结果表明,补偿后放大器的建立时间缩短了22.7%;当负载电容从0.5变化至2.5pF,其建立时间从3.62ns近似线性地增长到4.46ns;将采用该补偿方法的放大器应用于可变增益(VGA)系统,当闭环增益变化时,仅需调整MOS电容值仍可实现对应状态下的快速建立.     

高精度开关电流存储单元的设计

基于0.18-μm 1.8 V CMOS标准工艺,设计了一个高精度开关电流存储单元.通过设置存储晶体管工作于线性区,并结合虚拟开关等技术,降低了由阈值电压失配和时钟馈通所产生的谐波失真,有效消除了增益误差和漂移误差.利用Spectre仿真器,对版图进行后仿真验证.当输入信号频率为200 kHz、幅度为5μA、采样频率为5 MHz时,误差仅为0.5％,输入信号幅度低至1μA时,误差依然低于1％.仿真结果表明,电路具有高精度,可作为滤波器、∑-△调制器等系统的基本模块.     

一种采用新型时钟馈通补偿技术的栅电压自举开关

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.     

一种新型高性能开关电流存储单元的设计

利用一种新技术,在低压(1.8 V)条件下,设计了一种高性能的开关电流(SI)存储单元电路.该电路通过在基本存储单元基础上增加一个电压反转跟随器电路(FVF),从存储晶体管的输入端直接消除时钟馈通(CFT)误差电压,从而阻止了电流误差的产生,使得输出端的CFT误差电流降为原来的6%,并通过Hspice给出了仿真结果.结果表明所设计的电路方案正确有效.     

实现Folded-Cascode放大器快速建立的时钟馈通频率补偿

基于有源开关电容网络二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种用于Folded-Cascode放大器的频率补偿新方法,即通过MOS电容引入时钟馈通以调整电路阻尼因子η,使其达到MST状态,从而实现快速建立.研究结果表明,补偿后放大器的建立时间缩短了22.7%;当负载电容从0.5变化至2.5pF,其建立时间从3.62ns近似线性地增长到4.46ns;将采用该补偿方法的放大器应用于可变增益(VGA)系统,当闭环增益变化时,仅需调整MOS电容值仍可实现对应状态下的快速建立.     

一种高精度温度补偿型实时钟电路

设计了一种与环境温度变化无关、输出时钟频率保持恒定的温度补偿实时钟电路,可实现宽温度范围内(-40~85℃)时钟精度小于±5×10-6,即年累计计时误差小于2.5 min。该电路内置32.768 k Hz音叉型石英晶体振荡器,内置温度传感器可以定时检测器件温度,采用模拟和数字校准等温度补偿的方法可大幅度提高温度补偿精度和范围。该电路出厂时已经完成全温度范围内的温度校准,客户可直接使用。     

一种新的高性能开关电流排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

Complete Clock-Feedthrough Cancellation in Switched-Current Circuits by Combining the Replica Technique and the N-step Principle

This paper begins with an analysis of the charge injectionerror in the second-generation current memory cell. By combiningthe circuit-replication technique and the n-step principle, anew scheme for simultaneously cancelling both signal-dependentand signal-independent charge injection errors in second-generationswitched-current circuits is proposed. SPICE simulations areused to verify the feasibility and effectiveness of the proposedcell for tackling the charge injection problem. Major meritsof the proposed cell include capability to meet high precisionrequirements and applicability to any second-generation switched-currentcircuit configuration.     

A Current-to-Frequency Converter for Switched-Current Circuits

A current-to-frequency converter using switched-current (SI) circuits is proposed. The SI integrator with a hold-and-reset switch can control integration by the output signals. In the proposed circuit the oscillation frequency can be controlled by the input current, and the circuit is operated in the current domain. This is verified by HSPICE simulations.     

Clock-Feedthrough Compensated First-Generation SI Circuits and Systems

In this paper we discuss the clock-feedthrough problemin switched-current circuits. We present a clock-feedthroughcompensated first-generation SI memory cell that ideally cancelsboth constant and signal-dependent clock-feedthrough. It is shownhow to optimize the memory cell performance according to a generalcost function. Measured total harmonic distortion of the memorycell is less than -65 dB when optimized for low-power. The implementationof a second-order delta-sigma modulator using the presented memorycell is also described. Measurements confirmed a dynamic rangeof 11 bits. All circuits were implemented in a single-poly CMOSprocess.     

A 3.3 V, 10 Bits, Clock-Feedthrough Compensated Switched-Current Second Order Sigma-Delta Modulator

This article presents a low-pass sigma-delta modulator for Analogue-to-Digital conversion. The circuit uses a switched-current technique which presents a well known drawback called clock feedthrough. This phenomenon induces an error on the output signal value. In order to cancel the clock feedthrough effect, we use a new method based on a current feedback loop. The circuit is designed in 0.8 μm AMS “Austria Mikro Systems” single poly CMOS process. Measurements of the modulator are performed under A/D converters characterisation system, and show 55 dB dynamic range at 2.048 MHz sampling rate with 8 kHz input frequency bandwidth. These characteristics are suitable for audio applications.     

非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

非线性自动压扩的开关电流电路行为级建模方法

提出了一种新的基于非线性压扩函数自动构造的开关电流电路行为级建模方法,从而简化电路的建模和仿真.与原有的建模方法相比,该方法不仅可以对模型的误差分布进行有效地调控,而且能够降低模型的误差.为了验证本文所提出的行为级建模方法,对几种开关电流电路进行了建模和模拟试验.     

Wavelet Neural Network Approach for Testing of Switched-Current Circuits

Combining the time and frequency location and multiple-scale analysis of wavelet transform with the nonlinear mapping and generalizing of neural network, an efficient defect-oriented parametric test method using Wavelet Neural Network (WNN) for switched-current integrated circuits is proposed. Contraposing to the fully compatible digital CMOS technology and current scaling calculation of SI circuits, parameter cohort of switched current elements is used to compute the sensitivity and gain tolerance and is applied for selecting the test models. The selecting of the appropriate wavelet function based on particular switched current fault signal is discussed, and the number of network input and output nodes are determined by the circuit status and dimension of eigenvector which is the energy of wavelet decomposition coefficient. To simplify configuration of the neural network, the sampled data was preprocessed by wavelet transform. Illustrative examples show that the proposed wavelet neural network method for testing of switched current circuits is effective.