A comprehensive model for the I –V characteristics of metal-Ta 2 O 5 /SiO 2 -Si structures

The I–V characteristics of metal-Ta₂O₅/SiO₂-Si structures are precisely described with a comprehensive model, for both polarities, in the whole measurement range where there is no noticeable degradation and over seven orders of magnitude of the current. Hopping conduction and tunneling were elucidated to be the dominant conduction mechanisms in the SiO₂ layer and Poole–Frenkel internal field-assisted emission in the Ta₂O₅ layer. Other possible relevant mechanisms were discussed and subsequently discarded, based on their minor contribution. Theoretical calculations are made with fitted values of the defect related constants for hopping conduction of SiO₂ and Poole–Frenkel emission of Ta₂O₅ and the thickness of the SiO₂ layer. For gates positively biased, tunneling of electrons from the silicon conduction band through the SiO₂ is considered, while for gates negatively biased, tunneling of holes from the silicon valence band. Approximations for practical use are proposed and thus introduced limitations of the model discussed. The model is demonstrated on Al-insulator-Si structures containing thermally grown Ta₂O₅, previously studied in terms of microstructural, dielectric and electrical properties. The experimental results suggest that at higher current densities (>10 nA/cm²) an effect of compensation of the existing oxide charges by accumulated charges occurs. PACS 73.40.Qv; 73.50.-h; 73.61.-r; 77.55.+f     

Dielectric properties of Ta2O5 films grown on silicon substrates plasma nitrided in N2O

C–V characteristics and leakage currents of metal-insulator-silicon structures containing insulating film composed of thermally grown Ta₂O₅ and ultrathin SiO_xN_y layer grown in N₂O plasma were studied. Leakage in the structures is explained by tunneling in SiO_xN_y layer and Poole–Frenkel internal field assisted emission in Ta₂O₅. Theoretical calculations were made by known theoretical expression, while using fitted values of the thickness of SiO_xN_y, defect related constants for Ta₂O₅, and compensation degree r=1 for Ta₂O₅. For positive gate biases, tunneling of electrons from the silicon conduction band through SiO₂ is considered, while for gates negatively biased, tunneling of holes from the silicon valence band. In the early stage of nitridation barriers for injection decreases rapidly, then much slower. The thickness of the SiO_xN_y layer increases slowly with the nitridation time, as a result of the created barrier against diffusion of silicon atoms created by nitrogen incorporated at the interface between the silicon and oxide SiO_xN_y layer. PACS 73.40.Qv; 73.50.-h; 73.61.-r An erratum to this article can be found at .     

Effect of Ti doping on Ta2O5 stacks with Ru and Al gates

The Ti-doped Ta₂O₅ thin films (<10 nm) obtained by rf sputtering are studied with respect to their composition, dielectric and electrical properties. The incorporation of Ti is performed by two methods - a surface doping, where a thin Ti layer is deposited on the top of Ta₂O₅ and a bulk doping where the Ti layer is sandwiched between two layers of Ta₂O₅. The effect of the process parameters (the method and level of doping) on the elemental distribution in-depth of the films is investigated by the time of flight secondary ion mass spectroscopy (ToF-SIMS). The Ti and Ta₂O₅ are intermixed throughout the whole thickness but the layers are very inhomogeneous. Two sub-layers exist in all the samples — a near interfacial region which is a mixture of Ta-, Ti-, Si-oxides as well as TaSiO, and an upper Ti-doped Ta₂O₅ sub-layer. For both methods of doping, Ti tends to pile-up at the Si interface. The electrical characterisation is performed on capacitors with Al- and Ru-gate electrodes. The two types of MIS structures exhibit distinctly different electrical behavior: the Ru gate provides higher dielectric permittivity while the stacks with Al electrode are better in terms of leakage currents. The specific metal-dielectric reactions and metal-induced electrically active defects for each metal electrode/high-k dielectric stack define its particular electrical behavior. It is demonstrated that the Ti doping of Ta₂O₅ is a way of remarkable improvement of leakage characteristics (the current reduction with more than four orders of magnitude as compared with undoped Ta₂O₅) of Ru-gated capacitors which originates from Ti induced suppression of the oxygen vacancy related defects.     

Ionizing radiation effects on electrical and reliability characteristics of sputtered Ta2O5/Si interface

This paper describes the effect of ionizing radiation on the interface properties of Al/Ta₂O₅/Si metal oxide semiconductor (MOS) capacitors using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The devices were irradiated with X-rays at different doses ranging from 100?rad to 1?Mrad. The leakage behavior, which is an important parameter for memory applications of Al/Ta₂O₅/Si MOS capacitors, along with interface properties such as effective oxide charges and interface trap density with and without irradiation has been investigated. Lower accumulation capacitance and shift in flat band voltage toward negative value were observed in annealed devices after exposure to radiation. The increase in interfacial oxide layer thickness after irradiation was confirmed by Rutherford Back Scattering measurement. The effect of post-deposition annealing on the electrical behavior of Ta₂O₅ MOS capacitors was also investigated. Improved electrical and interface properties were obtained for samples deposited in N₂ ambient. The density of interface trap states (D_it) at Ta₂O₅/Si interface sputtered in pure argon ambient was higher compared to samples reactively sputtered in nitrogen-containing plasma. Our results show that reactive sputtering in nitrogen-containing plasma is a promising approach to improve the radiation hardness of Ta₂O₅/Si MOS devices.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

Charge trapping at Pt/high-k dielectric (Ta2O5) interface

A detailed analysis of the effects of constant low current injection was done, both in accumulation (J=0.001-0.2 mA cm⁻²) and in inversion (J=0.001-0.04 mA/cm²). The samples under investigation were metal-insulator-silicon structures containing high-k dielectric Ta₂O₅ radio frequency sputtered on p-type Si wafers, with Pt metal gate electrodes. The obtained results were compared with the ones obtained for Al gate samples. This experiment confirms the occurrence of charge trapping in the case of high-work-function Pt as metal. The effect has been attributed to emitting of electrons into the Pt conduction band during which creation of empty traps in the dielectric occurs, which then attract electrons injected in the dielectric. In order to examine the reversibility of the process, successive short runs as well as long runs (up to 10000 s) were performed.     

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal–oxide–semiconductor capacitor

In this study, GaAs metal–oxide–semiconductor (MOS) capacitors using Y‐incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 × 10¹¹ cm^–2 eV^–1), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 × 10^–5A/cm² at V_fb + 1 V). These merits should be attributed to the complementary properties of Y₂O₃ and Ta₂O₅:Y can effectively passivate the large amount of oxygen vacancies in Ta₂O₅, while the positively‐charged oxygen vacancies in Ta₂O₅ are capable of neutralizing the effects of the negative oxide charges in Y₂O₃. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices.

Capacitance–voltage characteristic of the GaAs MOS capacitor with TaYON gate dielectric (Y content = 27.6%) proposed in this work with the cross sectional structure and dielectric surface morphology as insets.     

Improved electrical properties of HfTiO/GeO x N y gate dielectric Ge MOS capacitors by using wet–NO Ge-surface pretreatment

Reactive cosputtering is employed to prepare high-permittivity HfTiO gate dielectric on n-Ge substrate. Effects of Ge-surface pretreatment on the interface and gate leakage properties of the dielectric are investigated. Excellent performances of Al/HfTiO/GeO _x N _y /n-Ge MOS capacitor with wet–NO surface pretreatment have been achieved with a interface-state density of 2.1×10¹¹ eV⁻¹ cm⁻², equivalent oxide charge of −7.67×10¹¹ cm⁻² and gate leakage current density of 4.97×10⁻⁵ A/cm² at V _g =1 V.     

Stress-induced leakage currents of the RF sputtered Ta2O5 on N-implanted silicon

The electrical (C-V and I-V) and reliability (constant current stress technique) properties of RF sputtered 30 nm thick Ta₂O₅ on N-implanted Si have been investigated. The dependence on the parameters of both Ta₂O₅ and the implanted interfacial layers on the stress time are discussed. The leakage current characteristics are analyzed by previously proposed comprehensive model. It is established that the reliability of the Ta₂O₅-based capacitors can be effectively improved if the Si substrate is a subject to preliminary N-implantation—markedly smaller stress induced leakage current as compared to the films on bare Si are detected. The stress mainly affects the properties of the interfacial layer and the generation of neutral traps is identified to be the primary cause for the stress-induced degradation. It is concluded that the implantation results in a strengthening of the interfacial layer against stress degradation.     

Impacts of Ti on electrical properties of Ge metal–oxide–semiconductor capacitors with ultrathin high-k LaTiON gate dielectric

Ge Metal–Oxide–Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La₂O₃ ratio, a suitable Ti/La₂O₃ ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×10¹¹ eV⁻¹ cm⁻², and relatively low gate-leakage current density of 2.0×10⁻³ A cm⁻² at a gate voltage of 1 V.     

On a current mechanism in Ta2O5 thin films

Electrical conduction in the temperature range of 120–370 K has been studied in sandwiched structures of Al/Ta₂O₅/Si. The tantalum oxide films were prepared by evaporation of tantalum on a p-Si crystal substrate, followed by oxidation at a temperature of 600°C. The temperature-dependent current-voltage (I–V) characteristics are explained on the basis of a phonon-assisted tunnelling model. The same explanation is given for I–V data measured on Ta₂O₅ films by other investigators. From the comparison of experimental data with theory the density of states in the interface layer is derived and the electron-phonon interaction constant is assessed.      

Growth and properties of epitaxial rare-earth scandate thin films

Epitaxial rare-earth scandate thin films of 100–1500 nm in thickness have been prepared by pulsed laser deposition on SrTiO₃(100) and MgO(100) substrates. Stoichiometry and crystallinity were investigated by Rutherford backscattering spectrometry/channelling (RBS/C), transmission electron microscopy, and X-ray diffraction. Electrical measurements on microstructured capacitors with a SrRuO₃ bottom electrode and Au top contacts reveal dielectric constants of 20 to 27, leakage currents of 0.85 to 6 μA/cm² at 250 kV/cm, and breakdown fields of 0.6 to 1.2 MV/cm. The optical bandgaps of the films range from 5.5 to 6 eV. The results substantiate the high potential of rare-earth scandates as alternative gate oxides. PACS 73.61.Ng; 73.40.Rw; 77.22.Ch; 77.55.+f; 78.40.Ha     

The effect of substrate material on the properties of tantalum oxide films

The effect of substrate material on the electrical characteristics of Ta _x O _y films produced by high-frequency magnetron sputtering of a tantalum oxide target is studied. The effect of oxygen plasma on leakage currents, dielectric permittivity, and dielectric dissipation factor of thin (300–400 nm) Ta _x O _y layers is found. It is proposed to process tantalum oxide films in oxygen plasma to control their electrical and dielectric properties.     

Improved performance of InGaZnO thin-film transistors with Ta2O5/Al2O3 stack deposited using pulsed laser deposition

Ta₂O₅/Al₂O₃ stacked thin film was fabricated as the gate dielectric for low-voltage-driven amorphous indium–gallium–zinc-oxide (IGZO) thin film transistors (TFTs). The Ta₂O₅/Al₂O₃ stacked thin film exhibits a combination of the advantages of Al₂O₃ and Ta₂O₅. The IGZO TFT with Ta₂O₅/Al₂O₃ stack exhibits good performance with large saturation mobility of 26.66 cm² V⁻¹ s⁻¹, high on/off current ratio of 8 × 10⁷, and an ultra-small subthreshold swing (SS) of 78 mV/decade. Such small SS value is even comparable with that of submicrometer single-crystalline Si MOSFET.     

Thermal stabilities of metal bottom electrodes for Ta2O5 metal-oxide-metal capacitor structure

Thermal stabilities of various metal bottom electrodes were examined by using a Ta₂O₅ metal-oxide-metal (MOM) capacitor structure. After depositing 10-nm thick Ta₂O₅ on metal-electrode/poly-Si, we performed rapid thermal oxidation (RTO) at 850 °C for 60 s in an O₂ ambient. A chemical-vapor-deposition (CVD) WSi₂ electrode showed satisfactory thermal stability after the RTO, while other examined electrode materials exhibited thermal degradation caused by oxidation failure or interfacial reaction between the substrate poly-Si and the Ta₂O₅. After post-annealing at 650 °C for 30 min (in N₂ condition) with CVD TiN top electrode, an effective oxide thickness (T_ox) of ∼32 Å and a leakage current density of ∼10⁷ A/cm² at 1.25 V were obtained from the MOM capacitor with the WSi₂ bottom electrode. Other electrode materials, such as TiN, TiSi_x, WN_x, W, and Ta, were severely oxidized during the RTO in the MOM structures, and very poor capacitor properties were obtained in terms of T_ox and leakage current.     

Current instabilities in dynamic random access memory storage capacitor formed with electron beam deposited Y2O3 dielectric

Metal-oxide-semiconductor (MOS) storage capacitors based on electron beam deposited Y₂O₃ extrinsic dielectric on Si show changes in capacitance density depending on the amorphous and crystalline phases. Bias stress cycle-dependent changes in capacitance density occur due to the non-equilibrium nature of defect states at the Y₂O₃/Si interface after O₂ annealing as a result of the emergence of a 4–8 nm thick SiO₂ film at the interface. Leakage currents show instability under repeated dc bias stress, the nature and extent of which depend upon the structure of the Y₂O₃ gate dielectric and the polarity of dc bias. With amorphous Y₂O₃, leakage currents drift to lower values under gate injection due to electron trapping, and to higher values under Si-injection due to the generation of holes. Though leakage current drift is minimal for crystalline Y₂O₃, its magnitude increases as the energy of injected electrons from mid-gap states is low and the local field due to asperity is high. The emergence of interfacial SiO₂ reduces the magnitude of Si-injection leakage current substantially, but causes transient changes resulting in switching to higher values at a threshold dc bias. Thermal detrapping of holes and reverse bias stress studies confirm that the instability of current is caused by an increase in the cathodic field from hole trapping at interface states. Leakage current instability limits the application of extrinsic high dielectric constant dielectrics in a high density DRAM storage capacitor, unless a new interface layer scheme other than SiO₂ and a method to form a defect-free dielectric layer can be implemented. Received: 29 October 2001 / Accepted: 22 April 2002 / Published online: 4 December 2002 RID="*" ID="*"Corresponding author. Fax: +1-413/545-4611, E-mail: rastogi@ecs.umass.edu     

Improvement of metal–ferroelectric–silicon structures without buffer layers between Si and ferroelectric films

Si-based metal–ferroelectric–semiconductor (MFS) structures without buffer layers between Si and ferroelectric films have been developed by depositing SrBi₂Ta₂O₉ (SBT) directly on n-type (100)-oriented Si. Some effective processes are adopted to improve the electrical properties of these MFS structures. Contrary to the conventional MFS structures with top electrodes directly on ferroelectrics, our MFS structures have been developed with thin dense SiO₂ films deposited between ferroelectric films and top electrodes. Due to the SiO₂ films, the leakage current densities of MFS structures are reduced to 2×10^-8 A/cm² under the bias of 5 V. The C-V electrical properties of the MFS structures are greatly improved after annealing at 400 °C in N₂ ambient for 1 h. The C-V memory windows are increased to 3 V, which probably results from the decrease of the interface trap density at the Si/SBT interface. Received: 7 September 1999 / Accepted: 24 November 1999 / Published online: 2 August 2000     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

Current conduction mechanisms of RF-Magnetron sputtered Y2O3 gate oxide on gallium nitride

Current conduction mechanisms through as-deposited and post-deposition annealed (200–800 °C) RF-magnetron sputtered Y₂O₃ gate oxides on n-type GaN have been systematically investigated with current–voltage measurements at temperature in the range of 25–175 °C. The possible current conduction mechanisms that govern the leakage current of Y₂O₃/GaN metal-oxide-semiconductor test structure are space-charge-limited conduction, Schottky emission, Poole–Frenkel emission, and Fowler-Nordheim tunneling. The dominance of these conduction mechanisms is depending on applied electric field and measurement temperatures.     

Improvement of electrical properties of low dielectric constant nanoporous silica films prepared using sol–gel method with catalyst HF

Microstructures and electrical properties of low dielectric constant (low-k) nanoporous silica films, prepared by sol–gel method using hydrofluoric acid (HF) replacing hydrochloric acid (HCl) as catalyst, have been investigated. It is found that the incorporation of HF effectively adjusts the hydrolysis and condensation of the tetraethoxylane based silica sols and makes the surface modification more sufficiently, leading to the increase of the porosity and the change in chemical bonds, and thus significantly improves the electrical properties of the films. The k value of 1.5 is reached in HF catalyzed films, which is much lower than that in HCl ones. The leakage current density are reduced to the lowest value of 6.12×10^-9 A/cm² in HF catalyzed films. It is determined that the Schottky emission occurs in HF catalyzed films, and both Schottky and Poole–Frenkel emissions occur in HCl ones, which may be due to the lower effective oxide charge density near the nanoporous silica and Si interfaces in HF catalyzed films than in HCl ones. PACS 72.20.Jv; 68.55.Jk; 61.43.Gt