Reduced pore diameter fluctuations of macroporous silicon fabricated from neutron‐transmutation‐doped material

The precision of photo‐electrochemical etching of perfectly‐ordered macropores in single‐crystalline silicon is limited by pore diameter fluctuations due to doping variations of the starting wafer (striations). The doping variation originates from the rotation during crystal growth in the float‐zone or Czochralski process, respectively. Experimentally, variations of the pore diameter up to 7% can occur. These so‐called striations limit performance of possible applications of macroporous silicon. As doping inhomogeneities are the reason for the striations, uniformly doped silicon wafers by neutron transmutation doping were used for the first time. Photoelectrochemical etching of neutron transmutated silicon has been carried out and the pore diameter fluctuation has been reduced by about 40% compared to standard doped float‐zone wafers. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Silicone oxidation for a‐Si:H passivation of wafers bonded to glass

A possible scenario for wafer‐based silicon photovoltaics is the processing of solar modules starting from thin silicon wafers bonded to glass. However, interactions between the adhesive used for bonding and the solar cell processing can affect the surface passivation of the bonded wafer and decrease cell performances. A method that suppresses these interactions and leads to state‐of‐the‐art a‐Si:H surface passivation is presented in this Letter. The method is based on an increase of the surface cross‐linking of a silicone adhesive by means of an O₂ plasma and it is successfully tested on three different silicones. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Probing high‐energy ion‐implanted silicon by micro‐Raman spectroscopy

The effect of ion implantation (4 MeV¹²C²⁺, 5 MeV¹⁶O²⁺, and 8 MeV²⁸Si²⁺) on [110] silicon wafers in channeling and random orientation is investigated by micro‐Raman spectroscopy. The profiles were measured using Scanning Electron Microscope (SEM) showing that the ions were penetrating deeper inside the wafer in the channeling case creating a 1–2 µm wide strongly modified region and agreeing with the d‐nuclear reaction analysis measurements. Micro‐Raman spectroscopy was employed for the assessment of the lattice damage, probing the side surface of the cleaved wafers at submicron step. The phonon modifications show strong lattice distortions in zones parallel to the front surface of the wafers and at depths, which agree with the results of the characterization techniques. In these strongly damaged zones, there is a substantial reduction in the phonon intensity, a small shift in wavenumber position, and a large increase in the phonon width. On the basis of a modification of the phonon confinement model that takes under consideration the laser beam profile, the reduction in intensity of scattered light, and the nanocrystallite size distribution from the simulation of the lattice displacements, the main characteristics of the Raman spectra could be reproduced for the random C and O implantations. The results indicate that at a critical doping level, the induced defects and lattice distortions relax by breaking the silicon single crystal into nanocrystallites, thus creating the observed zones of strongly distorted lattice. Copyright © 2014 John Wiley & Sons, Ltd.     

Aligned silicon nanowires with fine‐tunable tilting angles by metal‐assisted chemical etching on off‐cut wafers

The morphology control of aligned silicon nanowires (SiNWs) is highly desirable as SiNWs demonstrated high prospect in a variety of applications. Besides the control over length, shape and distribution of aligned SiNWs, the fine‐tuning of tilting angles thereof also attracted intense interest. Up to now, only several discrete tilting angles have been reported. In this Letter, the ability to fine‐tune the tilting angle of SiNWs is demonstrated and the range that can be achieved is identified. Our technique employs the anisotropic characteristic of the etching process using custom‐produced off‐cut Si wafers of various orientations as substrates. With this technique, a uniquely favoured etching direction can result and the tilting angle can be precisely controlled. Tilted SiNWs with tilting angles from 0° to 50° relative to the wafer normal were obtained. The mechanism of the tilting angle manipulation is also discussed. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

III‐V/silicon photonics for on‐chip and intra‐chip optical interconnects

In this paper III‐V on silicon‐on‐insulator (SOI) heterogeneous integration is reviewed for the realization of near infrared light sources on a silicon waveguide platform, suitable for inter‐chip and intra‐chip optical interconnects. Two bonding technologies are used to realize the III‐V/SOI integration: one based on molecular wafer bonding and the other based on DVS‐BCB adhesive wafer bonding. The realization of micro‐disk lasers, Fabry‐Perot lasers, DFB lasers, DBR lasers and mode‐locked lasers on the III‐V/SOI material platform is discussed.     

Specific features in the generation and motion of dislocations in heat-treated silicon wafers

The specific features in the generation and motion of dislocations in silicon single-crystal wafers after different heat treatments are investigated by the four-point bending technique. It is demonstrated that annealing of silicon single-crystal wafers at a temperature of 450°C leads to their substantial hardening as compared to the postgrowth state. The oxygen-containing precipitates and precipitate dislocation pileups formed in the silicon wafer bulk during multistage heat treatment are efficient heterogeneous nucleation sites of dislocations under the action of thermal or mechanical stresses. It is found that the multistage heat treatment of the silicon wafers under conditions providing the formation of an internal getter within their bulk results in considerable disordering of the wafer structure. The inference is made that the formation of the defect state in the crystal lattice of silicon and the strength characteristics of silicon wafers substantially depend on the temperature-time schedules of the low-temperature stage of multistage heat treatment.     

Improved control of the phosphorous surface concentration during in‐line diffusion of c‐Si solar cells by APCVD

Emitter formation for industrial crystalline silicon (c‐Si) solar cells is demonstrated by the deposition of phosphorous‐doped silicate glasses (PSG) on p‐type monocrystalline silicon wafers via in‐line atmospheric pressure chemical vapor deposition (APCVD) and subsequent thermal diffusion. Processed wafers with and without the PSG layers have been analysed by SIMS measurements to investigate the depth profiles of the resultant phosphorous emitters. Subsequently, complete solar cells were fabricated using the phosphorous emitters formed by doped silicate glasses to determine the impact of this high‐throughput doping method on cell performance. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

硅片及其太阳电池的光衰规律研究

采用氙灯模拟太阳光源,将光强调至1000 W/m2,研究常规太阳能级单晶硅片、多晶硅片和物理提纯硅片的原片、去损减薄片、热氧化钝化片、双面镀氮化硅(SiN x:H)膜钝化片、碘酒钝化片以及太阳电池的光衰规律.利用WT-2000少子寿命测试仪以及太阳电池I-V特性测试仪分别对硅片的少子寿命和太阳电池的I-V特性参数随光照时间的变化进行了测试.结果表明:所有硅片以及太阳电池在光照的最初60 min内衰减很快随后衰减变慢,180 min之后光衰速率变得很小,几乎趋于零.     

狭缝中蒸发水分子的红外吸收光谱（英文）

本文研究了硅片狭缝内水分子蒸发过程中的红外光谱吸收特性。通过改变相对于硅片狭缝的红外光偏振方向(水平:偏振方向与硅片狭缝方向平行;垂直:偏振方向与硅片狭缝方向垂直),测量了水分子在3900~3600 cm-1(伸缩振动)和1800~1400 cm-1(弯曲振动)的偏振红外光吸收。结果表明,经硅片间隙蒸发出来的水分子,在3900~3600 cm-1(伸缩振动)和1800~1400 cm-1(弯曲振动)区间,对垂直偏振光吸收较强,对水平偏振光吸收较弱,表明毛细效应导致蒸发的水分子偶极矩方向倾向于硅片狭缝的法线方向。     

Low‐Temperature Saw Damage Gettering to Improve Minority Carrier Lifetime in Multicrystalline Silicon

The minority carrier lifetime in multicrystalline silicon ? a material used in the majority of today's manufactured solar cells ? is limited by defects within the material, including metallic impurities which are relatively mobile at low temperatures (≤700 °C). Addition of an optimised thermal process which can facilitate impurity diffusion to the saw damage at the wafer surfaces can result in permanent removal of the impurities when the saw damage is etched away. We demonstrate that this saw damage gettering is effective at 500 to 700 °C and, when combined with subsequent low‐temperature processing, lifetimes are improved by a factor of more than four relative to the as‐grown state. The simple method has the potential to be a low thermal budget process for the improvement of low‐lifetime “red zone” wafers.

     

Plasma hydrogenated,reactively sputtered aluminium oxide for silicon surface passivation

The intentional addition of hydrogen during reactive sputtering of AlO_x films has led to a dramatic improvement of the surface passivation of crystalline silicon wafers achieved with this technique. The 5 ms effective minority carrier lifetime measured on 1.5 Ω cm n‐type CZ silicon wafers is close to the 6 ms of a control wafer coated by atomic layer deposition (ALD) of AlO_x. Hydrogen‐sputtered films also provide excellent passivation of 1 Ω cm p‐type silicon, as demonstrated by an effective lifetime of 1.1 ms. It is likely that the improved passivation is related to the formation of an interfacial silicon oxide layer, as indicated by FTIR measurements. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Asymmetric distribution of surface second harmonic generation for thin silver films deposited on Si(111)

The asymmetric distributions of surface optical second harmonic generation (SHG) through azimuthally angular scans of (111) silicon wafers on which thin silver films were deposited, have been detected with different polarizations of output beams. On account of the inversion symmetry of silicon crystals, the SHG for the Ag/Si system is mainly contributed by the silver film and the silicon surface. In this work, we found that the interface strain implies an asymmetric intensity variation of SHG with respect to the surface azimuthal angles as an ultra thin Ag film is deposited on silicon wafers. This asymmetric behavior is prominent as the deposited silver layer is heated so that the continuous film aggregates to become granular nanoparticles. Similar changes of the surface asymmetric SHG are observed for a bare Si wafer imposed upon by an external force.     

Dynamic photoluminescence lifetime imaging for the characterisation of silicon wafers

We present a fast and calibration‐free carrier lifetime imaging technique based on photoluminescence (PL) measurements using an InGaAs camera for the examination of crystalline silicon wafers. The carrier lifetime is determined from the time dependent luminescence emission after optical excitation. A ratio, including four PL images acquired at different times during the modulated excitation, is calculated and found to depend only on the camera integration time and the effective carrier lifetime. Therefore, the carrier lifetime is unambiguously determined by this ratio without knowing any additional wafer parameter. We demonstrate the applicability of the dynamic PL technique to multicrystalline silicon wafers. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Buried contact solar cell using tri-crystalline CZ silicon wafers

Tri-crystalline silicon wafers have been used for fabrication of buried contact solar cells. Optical properties and microstructures after texturing in KOH solution have been studied and compared with those of multi-crystalline silicon wafers. The textured surface of tri-crystalline wafer has a shape of V-groove with an angle of 109.48°. The efficiency of buried contact solar cell fabricated on tri-crystalline wafer measured to be 14.27% without optimization of cell process for tri-crystalline CZ wafer. Ray tracing computer simulations showed that V-groove composed of (1 1 1) after texturing can decrease reflectance significantly when cells are encapsulated. The reflectance can be reduced to about 4%, averaged over the 400–1100 nm wavelength range. The life time of tri-grain wafer was longer than that of multi-crystalline silicon wafer because it has only three twin boundaries in a wafer.     

Defect‐band photoluminescence imaging on multi‐crystalline silicon wafers

Defect‐band emission photoluminescence (PL) imaging with an indium‐gallium‐arsenide (InGaAs) camera was applied to multi‐crystalline silicon (mc‐Si) wafers, which were taken from different heights of different Si bricks. Neighboring wafers were picked at six different processing steps, from as‐cut to post‐metallization. By using different cut‐off filters, we were able to separate the band‐to‐band emission images from the defect‐band emission images. On the defect‐band emission images, the bright regions that originate from extend‐ ed defects were extracted from the PL images. The area fraction percentage of these regions at various processing stages shows a correlation with the final cell electrical parameters. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Electro‐optic Polymer Ring Resonator Modulator on a Flat Silicon‐on‐Insulator

Optical polymers are a promising material of choice in the development of hybrid silicon photonics devices. Particularly, recent progress in electro‐optic (EO) active polymers has shown a strong Pockels effect. A ring resonator modulator is a vital building block for practical applications, such as signal processing, routing, and monitoring. However, the properties of the hybrid silicon and EO polymer ring modulators are still far from their theoretical limits. Here, we demonstrate a unique design of a hybrid ring resonator modulator simply located onto a silicon‐on‐insulator (SOI) substrate. Extra doping and etching of the SOI wafer is not required, even so we measured an in‐device electro‐optic coefficient r₃₃ = 129 pm/V. The ring modulator exhibited a high sensitivity of the electrically tunable resonance, which enabled a 3 dB bandwidth of up to 18 GHz. The proposed technique will enable efficient mass‐production of the micro‐footprint modulators and promote the development of integrated silicon photonics.     

Simulation of the stresses produced in large-diameter silicon wafers during thermal annealing

The three-dimensional problem of stress and strain fields in dislocation-free silicon wafers 200 and 300 mm in diameter placed horizontally on three symmetrical supports and subjected to is gravitational forces and thermal stresses formulated and solved in the isotropic approximation. Under the action of gravitational forces, a wafer is shown to have the lowest total stress when the supports are positioned at a distance of 0.6–0.7R from the center of the wafer. The shear-stress fields are calculated for all possible slip systems. The elastic-stress field in a 300-mm wafer is found to be induced mainly by gravitational forces even at a radial temperature gradient of 10 K. At this temperature gradient, the contribution from thermal stresses in a 200-mm wafer is comparable to the contribution from gravitational forces. At radial temperature gradients lower than 5 K, the contribution from thermal stresses can also be neglected for a 200-mm wafer. The maximum shear stresses calculated indicate that one should not neglect possible dislocation generation in the zone of contact between a wafer and the supports during high-temperature annealing of 200-mm and, especially, 300-mm wafers.     

Photoconductance‐calibrated photoluminescence lifetime imaging of crystalline silicon

We use photoluminescence (PL) measurements by a silicon charge‐coupled device camera to generate high‐resolution lifetime images of multicrystalline silicon wafers. Absolute values of the excess carrier density are determined by calibrating the PL image by means of contactless photoconductance measurements. The photoconductance setup is integrated in the camera‐based PL setup and therefore identical measurement conditions are realised. We demonstrate the validity of this method by comparison with microwave‐detected photoconductance decay measurements. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

19.4%‐efficient large‐area fully screen‐printed silicon solar cells

We demonstrate industrially feasible large‐area solar cells with passivated homogeneous emitter and rear achieving energy conversion efficiencies of up to 19.4% on 125 × 125 mm² p‐type 2–3 Ω cm boron‐doped Czochralski silicon wafers. Front and rear metal contacts are fabricated by screen‐printing of silver and aluminum paste and firing in a conventional belt furnace. We implement two different dielectric rear surface passivation stacks: (i) a thermally grown silicon dioxide/silicon nitride stack and (ii) an atomic‐layer‐deposited aluminum oxide/silicon nitride stack. The dielectrics at the rear result in a decreased surface recombination velocity of S_rear = 70 cm/s and 80 cm/s, and an increased internal IR reflectance of up to 91% corresponding to an improved J_sc of up to 38.9 mA/cm² and V_oc of up to 664 mV. We observe an increase in cell efficiency of 0.8% absolute for the cells compared to 18.6% efficient reference solar cells featuring a full‐area aluminum back surface field. To our knowledge, the energy conversion efficiency of 19.4% is the best value reported so far for large area screen‐printed solar cells. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review

Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.