A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂ /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson’s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson’s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.     

A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel

A unified charge-based model for fully depleted silicon-on-insulator (SOI) metal–oxide semiconductor field-effect transistors (MOSFETs) is presented. The proposed model is accurate and applicable from intrinsic to heavily doped channels with various structure parameters. The framework starts from the one-dimensional Poisson–Boltzmann equa- tion, and based on the full depletion approximation, an accurate inversion charge density equation is obtained. With the inversion charge density solution, the unified drain current expression is derived, and a unified terminal charge and intrinsic capacitance model is also derived in the quasi-static case. The validity and accuracy of the presented analytic model is proved by numerical simulations.     

Equivalent Trap Energy Level Extraction for SiGe Using Gate-Induced-Drain-Leakage Current Analysis

The gate-induced-drain-leakage of MOSFETs is analyzed to better understand the sub-threshold swing degradation of SiOe tunnel field-effect transistors and their band-to-band tunneling mechanism. The numerical model of the analysis is elaborated. Equivalent trap energy levels are extracted for Si and strained SiOe. It is found that the equivalent trap energy level in SiGe is shallower than that in Si.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

A Closed-Form Model for Position-Dependent Potential across the Channel in DG-MOSFETs

A closed-form model for electrostatic potential distribution in the direction normal to the channel for double-gate （DG） MOSFETs is presented. The effects of doping （NA for nMOS） and minority carriers both are taken into account for the first time, in solving Poisson＇s equation analytically. Excellent agreement between model-predicted results and numerical device simulation is achieved for a wide range of body thickness, light or high channeldoping, under various bias conditions. This complete closed form for position-dependent potential distribution has wide applications for MOS compact modelling and device design.     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

A threshold voltage model MOSFETs considering for high-k gate-dielectric fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

As the channel length of metal-oxide-semiconductor field-effect transistors （MOSFETs） scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate （SG） nMOSFET is developed. The SchrSdinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The eentroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.     

HYBRID ORBITALS OF CARBON ATOMS IN THE D6hC36 MOLECULE UNDER THE ROTATING ELLIPSOID MODEL

The hybrid orbitals of carbon atoms in the D_6h C₃₆ molecule are studied using two rotating ellipsoid models. The model 1 is 1.66R for the short semi-axis and 2.34R for the long semi-axis, and the model 2 is 1.78R and 2.26R respectively, where R is the C-C bond length. By comparison,we think the model 2 to be more proper in revealing the electronic properties of the D_6h C₃₆ molecule. The component of s orbitals in the π states hybridized for each of the atoms is much larger than C₆₀, in which the s-orbit component is 0.0380 and the p-orbit is 0.9620. The most component is 0.2098 and the least is 0.0482 for model 1; the most is 0.1764 and the least is 0.0656 for model 2.     

A Quasi-3D Threshold Voltage Model for Dual-Metal Quadruple-Gate MOSFETs

Due to challenges with relentless scaling of conventional bulk complementary metal-oxide- semiconductor （CMOS） devices, non-conventional CMOS devices have been of great interest to scale metaboxide-semiconductor field effect transistors （MOSFETs） to the 32nm gate length and below effectively. Among non-conventional CMOS devices, quadruple-gate （QG） MOSFETs have been gaining interest because they are sup- posed to provide excellent electrostatic controllability for ultra-large-scale integration （ULSI） applications. A number of attempts have been made to analyze QG MOSFETs analytically with a great amount of success. Sharma et al. have presented an an- alytical threshold voltage model for QG MOSFETs using an isomorphic polynomial function for solv- ing the 3D Poisson equation. Chiang has presented a number of models of scaling length,threshold voltage and subthreshold current for QG MOS- FETs adopting a concept of the so-called equivalent number of gates （ENGs）.     

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metal- oxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H+ generated during NBTI stress.     

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal--Oxide--Semiconductor Field Effect Transistor

A novel fully depleted air A1N silicon-on-insulator （SOD metai-oxide-semiconductor field effect transistor （MOS- FET） is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75K higher than the atmosphere temperature, while the lattice temperature is just 4 K higher than the atmosphere temperature resulting in less severe self-heating effect in air A1N SOI MOSFETs and A1N SOI MOSFETs. The on-state current of air A1N SOI MOSFETs is similar to the A1N SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of A1N SOI is 6. 7 times of normal SOI MOSFETs, while the counterpart of air A1N SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air A1N SOl MOSFETs with different drain voltage is much less than that of A1N SOI devices, when the drain voltage is Mased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured.     

Analytical analysis of surface potential for grooved-gate MOSFET

The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner $\theta _0 $. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect (SCE) immunity.     

One-dimensional continuous analytic potential solution to generic oxide-silicon-oxide system

A one-dimensional continuous analytic potential solution to a generic oxide--silicon--oxide system is developed. With the analytic solution, the potential distribution in the silicon film is predicted. A physics-based relation between surface potentials is also derived and then applied to the generic oxide--silicon--oxide metal--oxide--semiconductor field-effect transistors (MOSFETs) for the calculation of surface potentials     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.