Thickness scaling limitation factors of ONO interpoly dielectricfor nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule     

High quality interpoly dielectrics deposited on thenitrided-polysilicon for nonvolatile memory devices

High quality interpoly dielectrics have been fabricated by using NH₃ and N₂O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silicate (TEOS) oxide with N₂O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics. The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simultaneously improve both charge-to-breakdown (up to 20 C/cm² ) and electric breakdown field (up to 17 MV/cm)     

Polyoxide thinning limitation and superior ONO interpoly dielectricfor nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate     

New scaling guidelines for MNOS nonvolatile memory devices

New phenomena in MNOS retention characteristics that originate from stored charge distribution are described and new scaling guidelines are indicated. The most significant phenomenon is that write-state retentivity is less dependent on the programmed depth, and is improved by reducing silicon nitride thickness. This behavior suggests that write-state charges are distributed rectangularly, while erase-state charges are distributed exponentially. The lower limit of the programming voltage is determined by write-state retentivity and not erase-state retentivity, and the write-state charge distribution depth determines the lower limit of silicon nitride thickness. The upper limit of the programming voltage is determined by erase-state retentivity after erase/write cycles. The scaling guidelines indicate that 16-Mb EEPROMs can be designed using MNOS memory devices     

Multi-layer high-κ interpoly dielectric for floating gate flash memory devices

We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO₂ were studied. It is shown that compared with a conventional Al₂O₃–HfO₂–Al₂O₃ high–low–high barrier structure, the HfO₂–Al₂O₃–HfO₂ multilayer IPD stack with a low–high–low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high-κ IPD.     

Gadolinium-based metal oxide for nonvolatile memory applications

In this study, the memory characteristic of a gadolinium (Gd)-based oxide charge storage layer was demonstrated. The metal/oxide/high-k/oxide/silicon (MOHOS)-type memories were fabricated by using two different charge storage layers. The Gd₂O₃ nanocrystal (Gd₂O₃-NC) was used as a charge storage layer due to the discrete nodes, while the HfGdO high-k material was used as a charge storage layer due to the existence of discrete traps. In the case of Gd₂O₃-NC memory, a combination of X-ray photoelectron spectroscopy (XPS) and ultraviolet (UV)–visible spectrophotometer analysis was used in this study to extract the valence band location and the band-gap of the Gd₂O₃-NC layer. The retention characteristic was also analyzed to extract the trapping level in Gd₂O₃-NC, based on the relationship between trapping energy and discharging time. A band diagram was created to characterize the memory effect of the Gd₂O₃-NC memory. In the case of HfGdO SONOS-type memory, the electrical and physical studies were conducted for HfGdO charge-trapping layers deposited by a dual-sputtered method for silicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile memory. The Hf/Gd dual-sputtered power ratio and the Ar/O₂ gas flow ratio were optimized. It was observed that the nonstoichiometric GdO (2 0 0) structure may be the main charge-trapping site for the memory. The memory samples with Hf/Gd = 150/150 and Ar/O₂ = 20/5 exhibited better electrical performance. A physical model is proposed to further explain the retention mechanism.     

Resistance switching of the nonstoichiometric zirconium oxide for nonvolatile memory applications

The resistance switching behavior and switching mechanism of nonstoichiometric zirconium oxide thin films were investigated for nonvolatile memory application. The Pt/ZrO/sub x//p/sup +/-Si sandwich structure fabricated by reactive sputtering shows two stable resistance states. By applying proper bias, resistance switching from one to another state can be obtained. The composition in ZrO/sub x/ thin films were confirmed from X-ray photoelectron spectroscope (XPS) analysis, which showed three layers such as top stoichiometric ZrO/sub 2/ layer with high resistance, transition region with medium resistance, and conducting ZrO/sub x/ bulk layer. The resistance switching can be explained by electron trapping and detrapping of excess Zr/sup +/ ions in transition layer which control the distribution of electric field inside the oxide, and, hence the current flow.     

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2–4 × 10¹¹ cm⁻², diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO₂ interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.     

Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory

Introduction of high-k dielectrics in Flash memory is seen as a must for the upcoming technology nodes. Hafnium aluminate (HfAlO) has been identified as a possible candidate for implementing the interpoly dielectric in floating gate memory. In this work, we establish a link between the material morphology and its electrical response, allowing to understand memory device behavior and to consequently assess the potential and limitations of HfAlO as IPD in a memory cell.     

MNOS/CCD nonvolatile analog memory

MNOS storage sites have been integrated with an n-channel CCD to produce a nonvolatile memory capable of storing sampled analog signals. Analog signals, sampled at the CCD input, are stored as trapped charge in the MNOS dielectric and may be replicated nondestructively after four days of storage with a linear dynamic range of 33 dB.     

Long-term electron leakage mechanisms through ONO interpoly dielectric in stacked-gate EEPROM cells

Analyzing the measured shift rate of cell threshold-voltage, we have studied the long-term electron leakage mechanisms through an oxide-nitride-oxide (ONO) interpoly dielectric, which causes reliability problems due to the degradation of the data retention characteristics in the stacked-gate Flash EEPROM devices. The cell threshold-voltage shifts were measured as a function of bake time at various temperatures by the high-temperature accelerated test. Based on the experimental results, a new empirical model was developed and evaluated. It can explain the dominant mechanisms for the spontaneous charge leakage through an ONO interpoly dielectric for the long-term phase. The model clearly shows that cell threshold-voltage shifts during the baking test are caused predominantly by the thermally activated direct-tunneling when electrons, after escaping from the internitride trap-sites near the top oxide of ONO layer by the thermionic emission mechanism, finally tunnel through the thin top oxide to the control gate. This interpretation is strongly supported by the V/sub T/-shift and temperature dependence of the V/sub T/-shift rate, showing that the simulation results are well fit to the experimental data.     

Resistive switching characteristics of Sm2O3 thin films for nonvolatile memory applications

This study investigates a sputtered Sm₂O₃ thin film to apply into a resistive random access memory device. The proposed device exhibits a stable resistance ratio of about 2.5 orders after 10⁴ cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85 °C. The conduction mechanisms for low and high resistance states are dominated by ohmic behavior and trap-controlled space-charge limited current, respectively. The resistance switching is ascribed to the formation/rupture of conductive filaments.     

Morphology control of tunneling dielectric towards high-performance organic field-effect transistor nonvolatile memory

We report high-performance organic field-effect transistor nonvolatile memory based on nano-floating-gate, which shows a large memory window of about 70 V, high ON/OFF ratio of reading current over 10⁵ after 1 week storage, high field-effect mobility of 0.6 cm²/V s, and good programming/erasing/reading endurance. The devices incorporate Au nanoparticles and polystyrene layer on top to form the nano-floating-gate, and we demonstrate that the morphology control of the tunneling dielectric is critically significant to improve the memory performance. The optimized tunneling dielectric morphology is favorable to the efficient charge tunneling, reliable charge storage and high-quality organic film growth.     

Plasma etching optimization of oxide/nitride/oxide interpolydielectric breakdown time in flash memory devices

The breakdown time of flash memory oxide/nitride/oxide (ONO) layer t_bd under positive constant current stressing has been found to be closely related to the cumulative extent of (over)etch of the tungsten silicide, control polysilicon, and ONO layers, i.e., Σ(ΛOE). An empirical first-order relation between t_bd and Σ(ΛOE) has been derived to facilitate the plasma etch recipe optimization. This has led to a four-fold increase in the average t_bd across a 200-mm wafer to 208 s. More importantly, the spread in t_bd has been tightened to ~5%, which is down from ~54%     

Determination of the Fowler-Nordheim tunneling barrier from nitride to oxide in oxide:nitride dual dielectric

Using a simple but novel method of analysis, the voltage drop across the oxide (pad-oxide) in the oxide:nitride dual dielectric is determined for both positive and negative gate polarities. From the Fowler-Nordheim plot of the oxide voltage drop, the electron barrier from nitride to oxide is 3.2 ± 0.2 eV. However, the current injection from the nitride electrode is about 7 orders of magnitude lower than the current injection from the silicon electrode under the same oxide field values. This large field-current difference between the two directions of electron injection is consistent with the large difference observed in the J ★ t (charge fluence to breakdown) data.     

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.     

JVD silicon nitride as tunnel dielectric in p-channel flash memory

High-quality jet vapor deposition nitride is investigated as a tunnel dielectric for flash memory device application. Compared to control devices with SiO₂ tunnel dielectric, faster programming speed as well as better retention time are achieved with low programming voltage. The p-channel devices can be programmed by hot electrons and erased by hot holes, or vice versa. Multilevel programming capability is shown     

High-quality oxide/nitride/oxide gate insulator for GaN MISstructures

We report on a SiO₂/Si₃N₄/SiO₂ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450°C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150°C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs     

Starch as ion-based gate dielectric for oxide thin film transistors

Application of nature bio-materials in electronics represents an emerging field of science and technology that began a few years ago. For the dielectric of transistors, the ion-based electric double layer (EDL) gating has becoming the widely accepted theory of charge modulation with hydrated bio-polymer dielectrics. Herein, we report on the use of starch as the ion-based gate dielectric for oxide thin film transistors. Two types of starches, i.e., water-soluble starch and potato starch were studied either with or without the incorporation of glycerol. Important parameters including mechanical strength, surface morphology, specific capacitance and ion conductivity were analyzed in accordance with the molecular structure of starches. The transistor performance was found in close relation with the specific capacitance and ion conductivity of the starch dielectrics. Higher on/off ratio (2.6 × 10⁶) and field mobility (0.83 cm²V⁻¹s⁻¹) were obtained with glycerol incorporated potato starch due to the advantage in capacitance and ion conductivity. Lower ion conductivity of the water-soluble starch on the other hand caused the large current hysteresis, so the current retention property was examined for the potential application as a memory element. Collectively, this work solidifies our knowledge on the material type, EDL gating mechanism and applicability of nature bio-material gated transistors.     

ZnO as a dielectric for organic thin film transistor-based non-volatile memory

This paper demonstrates the novel application of d.c. sputtered zinc oxide (ZnO) as a charge trapping dielectric material for the application of an organic thin film transistor (OTFT) based non-volatile memory (NVM). The motivation of using ZnO as a dielectric is due to its chemical stability and optical transparency, enabling future development of transparent electronic devices. Unbalanced magnetron d.c. sputtering with Ar:O₂ ratio of 80:20 was used to obtained a ZnO dielectric of 50 nm thick. The ZnO has an optical band gap of 3.23 eV, resistivity and k-value of 5 × 10⁷ Ω-cm and 50, respectively. The ZnO sandwiched between two layers of low-k methyl-silsesquioxane (MSQ) sol–gel dielectric creates a triple layer dielectric structure for charge storage. A solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene, was used as an active layer of an OTFT-NVM. It has been successfully demonstrated that this OTFT-NVM can be electrically programmed and erased at a low voltage.