A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-/spl mu/m CMOS

This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54/spl deg//1.1/spl deg/ for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

A 1.8-V 2.4/5.15-GHz dual-band LCVCO in 0.18-/spl mu/m CMOS technology

A dual band, fully integrated, low phase-noise and low-power LC voltage-controlled oscillator (VCO) operating at the 2.4-GHz industrial scientific and medical band and 5.15-GHz unlicensed national information infrastructure band has been demonstrated in an 0.18-/spl mu/m CMOS process. At 1.8-V power supply voltage, the power dissipation is only 5.4mW for a 2.4-GHz band and 8mW for a 5.15-GHz band. The proposed VCO features phase-noise of -135dBc/Hz at 3-MHz offset frequency away from the carrier frequency of 2.74GHz and -126dBc/Hz at 3-MHz offset frequency away from 5.49GHz. The oscillator is tuned from 2.2 to 2.85GHz in the low band (2.4-GHz band) and from 4.4 to 5.7GHz in the high band (5.15-GHz band).     

A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A dual-mode transceiver integrates the transmitter of 0-dBm output power and the receiver for both Bluetooth with -87 dBm sensitivity and 802.11b with -86 dBm sensitivity in a single chip. A direct-conversion architecture enables the maximum reuse and the optimal current consumption of the various building blocks in each mode for a low-cost and low-power solution. A single-ended power-amplifer (PA) driver transmits the nominal output power of 0 dBm with 18-dB gain control in 3-dB steps. Only little area overhead is required in the baseband active filter and programmable gain amplifier (PGA) to provide the dual-mode capability with optimized current consumption. The DC-offset cancellation scheme coupled with PGAs implements the very low high-pass cutoff frequency with a smaller area than required by a simple coupling capacitor. Fabricated in 0.25-/spl mu/m CMOS process, the die area is 8.4 mm/sup 2/ including pads, and current consumption in RX is 50 mA for Bluetooth and 65 mA for 802.11b from a 2.7-V supply.     

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.     

A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.     

A fully integrated SOC for 802.11b in 0.18-/spl mu/m CMOS

A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.     

A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

A 0.3-25-GHz ultra-wideband mixer using commercial 0.18-/spl mu/m CMOS technology

An ultra-wideband mixer using standard complementary metal oxide semiconductor (CMOS) technology was first proposed in this paper. This broadband mixer achieves measured conversion gain of 11 /spl plusmn/ 1.5 dB with a bandwidth of 0.3 to 25 GHz. The mixer was fabricated in a commercial 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation. It also presented better gain-bandwidth-product performance compared with that of GaAs-based HBT technologies. The chip area is 0.8 /spl times/ 1 mm/sup 2/.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-/spl mu/m CMOS technology

A frequency synthesizer incorporating one single-sideband (SSB) mixer generates seven bands of clock distributed from 3 to 8GHz with 1-ns switching time. An efficient frequency synthesizing technique producing balanced bands around one center frequency is employed, and the SSB mixer uses double degeneration topology to increase the linearity. Fabricated in 0.18-/spl mu/m CMOS technology, this circuit achieves a sideband rejection of 37 dB while consuming 48 mW from a 2.2-V supply.