Dynamic effects in the detection of bridging faults in CMOS ICs

Dynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors < T ₀, T ₁ >, in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T₀ initializes the faulty signal to a logic value different from the fault-free one produced by T ₁. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector.     

Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

On local transformations and path delay fault testability

Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered.Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced.Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a pattern to be searched and a matched subcircuit can be weakened to allow the application of local transformations more frequently.Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.This work was supported in part by DFG grants Be 1176/4-1, Be 1176/4-2 and SFB 124 VLSI Design Methods and Parallelism.     

A 2.4-GHz CMOS Monolithic VCO with an MOS Varactor

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8m CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about –118 dBc/Hz at 1 MHz from the carrier.     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a g_m/I_D based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

Design of a CMOS closed-loop system with applications to bio-impedance measurements

This paper proposes a method for impedance measurements based on a closed-loop implementation of CMOS circuits. The proposed system has been conceived for alternate current excited systems, performing simultaneously driving and measuring functions, thanks to feedback. The system delivers magnitude and phase signals independently, which can be optimized separately, and can be applied to any kind of load (resistive and capacitive). Design specifications for CMOS circuit blocks and trade-offs for system accuracy and loop stability have been derived. Electrical simulation results obtained for several loads agree with the theory, enabling the proposed method to any impedance measurement problem, in special, to bio-setups including electrodes.     

2.1 GHz射频CMOS混频器设计

设计了一个用于第三代移动通信的2.1 GHz CMOS下变频混频器,采用TsMC 0.25 μm CMOS工艺.在设计中,用LC振荡回路作电流源实现低电压;并用增大电流和降低跨导的方法提高线性度.在Cadence RF仿真器中对电路进行了模拟,在1.8 V电源电压下,仿真结果为:1 dB压缩点PtdB-10.65 dBm,lIP3 1.25 dBm,转换增益7 dB,噪声系数10.8 dB,功耗14.4 mW,且输入输出端口实现了良好的阻抗匹配.并用Cadence中的Virtuoso Layout Editor软件绘制了电路的版图.     

Logic Synthesis with High Speed CMOS Circuit Techniques

Systems for automated logic synthesis with the True Single Phase Clocking circuit technique (TSPC) and a modified form of the Clock and Data Precharged Dynamic (CDPD) circuit technique, are presented. The CDPD system synthesizes high speed one clock cycle modules of unate Boolean functions in short design time. A novel true single phase clocking (TSPC) flip-flop suitable for CDPD synthesis simplifies interfacing with standard edge triggered clocking schemes. Also, a TSPC cell library for automatic logic synthesis with the TSPC circuit technique is presented. The library is targeted for high performance DSP applications. Fabricated test circuits synthesized by both the CDPD and TSPC synthesis systems in a 0.8m standard CMOS process are described and their performance is verified. Clock frequencies up to 700MHz were measured.     

Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits

In this paper we analyze fault behaviors of internal feedback bridging faults. To investigate their behaviors, we use a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results, we find that behaviors of internal feedback bridging faults are more complex than those of external feedback bridging faults. We expose that they cause IDDQ-only failure, internal latch and internal oscillation as well as latch and oscillation behavior. These phenomena are caused by the following facts: formation of an electrically conducting feedback loop and connection of the feedback loop with the circuit output depend on input values of the circuit, and the feedback loop is often alive only within the circuit. We also discuss methods for detecting this kind of fault.     

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.Partially presented at the VLSI Test Symposium, Atlantic City, 1992.     

新型低噪声电流型CMOS边沿触发器设计

提出以电流信号表示逻辑值的新型低噪声触发器设计,用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。所提出的设计包括主从型边沿触发器和单闩锁单边沿触发器。单个锁存器的电流型边沿触发器设计是通过在有效时钟沿后产生的窄脉冲使锁存器瞬时导通完成一次取样求值。与主从型触发器相比,单闩锁结构的触发器具有结构简单、直流功耗低的特点。采用0.25μm CM O S工艺参数的HSP ICE模拟结果表明,所提出的电流型触发器工作时,在电源端产生的电流波动远远小于传统的CM O S电路。     

电流型CMOS多值乘法器分析与芯片的设计

本文以电流型ＣＭＯＳ电路为基础，提出了种一高速、高集成度的多值乘法器设计方案，讨论了多值乘法器与集成度、速度和精度的关系，同时用改进ＣＭＯＳ工艺实现了３×３位８值乘法器的设计，得到了较理想的结果。     

一种基于模型的测试性分析评估方法

产品可测试性设计是否满足测试性要求需要进行测试性分析和评估,基于模型的测试性分析评估方法因为它独特的优势被广泛用于产品测试性辅助分析之中。针对多层次系统产品的结构功能特点,提出一种基于相关性数学模型和多信号流图模型的测试性建模分析评估方法。该方法分析目标系统的测试性模型要素,建立了两测试性模型,以测试性工程和维修系统软件(TEAMS)为平台,通过软件仿真评估对模型进行校验,使其符合真实系统的故障传播关系和故障定位过程,在此基础上改进测试性设计,使其达到测试性定量指标。运用该方法对某装备电子系统部分进行实例分析,仿真结果验证了该方法的有效性和可行性,结论表明:基于相关性数学模型和多信号流图模型的测试性建模方法能够满足装备电子系统的测试性分析评估需求。     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

CMOS/SOS集成电路输入保护电路设计

本文描述了一种CMOS/SOS集成电路输入保护电路的设计方法。根据保护电路原理,计算了不同保护电路的保护能力,并用实验加以证实。     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

Novel Architectures of Class AB CMOS Mirrors with Programmable Gain

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5- m CMOS technology with ±1 V supplies are shown that validate the proposed circuits.     

Design tradeoffs for sub-mW CMOS biomedical limiting amplifiers

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35 μm CMOS technology to operate over dc to 20 MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 72 dB.