Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.     

基于码密度统计的流水线模数转换器校准算法研究

本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分,只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码,该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示,转换器的积分非线性由90LSB下降到0.8LSB,微分非线性由2LSB下降到0.3LSB;信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。     

流水线ADC设计中的数字校准算法与实现

数字校准是高速高精度流水线ADC设计中的关键技术之一。文章提出了一种可通过校准控制生成测试信号,自动计算权重来对流水线ADC中电容失配进行误差补偿的技术。该技术能有效地减小增益有限、电荷注入等非理想因素的影响,使校准输出后的数据拥有更高的准确度,提高了系统的线性度。     

一款结合数字校正技术的流水线ADC设计

基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。     

Digital background calibration of capacitor mismatches and harmonic distortion in pipelined ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.     

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18 μm CMOS process.     

一种基于统计的流水线ADC数字后台校准方法

高精度流水线ADC的设计需要校准技术来提高其转换精度.基于统计的数字后台校准方法无需校准信号,直接通过对输出的统计得到误差值的大小,将其从数字输出中移除从而消除了ADC输出非线性.将该校准方法应用于14bit流水线ADC中,仿真结果表明校准后信噪失真比SNR为76.9dB,无杂散动态范围SFDR为73.9dB,有效精度ENOB从9bit提高到12.5bit.     

A fast foreground digital calibration technique for pipelined ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.     

采用后台数字校准的12位100MHz流水线模数转换器

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.     

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3×1.6 mm~2, and consumes 205 mW at 1.8 V.     

电容误差平均技术在流水线ADC中的应用

随着流水线ADC精度的不断提高,其转换器性能受到各种电路非线性的严重影响.电容失配是引起非线性的一种主要因素.实践表明,电容误差平均技术是消除失配误差的一种有效途径.介绍几种重要的电容误差平均方法的原理和工作方式,并指出各自存在的优缺点.最后对误差校准技术的发展趋势进行分析与展望.     

A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs

A pseudo-background continuous-time strategy is developed for gain and offset calibration in open-loop inter-stage residue amplifiers of pipeline ADCs. The ping-pong calibration strategy is enhanced for loop gain and accuracy to be utilized for open-loop RAs. Thanks to a reliable technique for preserving analog voltages for long time durations, data conversion continuously proceeds. In addition, other advantages of the foreground techniques, like lower power consumption and smaller area are achieved. The reduction in power consumption due to the elimination of a wide-bit digital processor easily overcomes the increase which stems from the replica residue amplifier. Storing the calibration results in reliable analog storages, the multiplexing frequency and clock frequency within the calibration loop are reduced to 100 KHz, respectively, which result in a significant amount of power reduction. Monte-Carlo analysis for 100 iterations shows that the calibration loop provides an absolute gain of 4 with the median value of 3.996 and standard deviation of 0.003, while the threshold voltages and reference levels experience a Gaussian distribution with 25 mV variations at 3σ. Total power consumption equals 1.8 mW for both the offset and gain calibration at 1.8 V (and 3.3 V for DAC) supply voltage. More than 9-bit accuracy is obtained at 50 mV peak-to-peak residue. Linearity is reduced to 7-bits for full-swing input range. Also, 13 dB and 8 dB improvement in SNDR and SFDR of a 13-bit 100S/s pipeline ADC is achieved when the offset and gain calibration loops are activated. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 μm CMOS technology.     

All-digital background calibration technique for timing mismatch of time-interleaved ADCs

An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system.     

A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture

The paper introduces a sub-binary architecture in 16-bit split-capacitor successive-approximation register (SAR) analog-to-digital converters (ADCs). The redundancy in sub-binary capacitors array provides ways to correct the dynamic errors in conversion procedure with a smaller overall conversion time. So the redundancy can be used to solve the mismatch or parasitic problems in split-capacitor CDAC SAR. A background digital calibration method with perturbation is utilized to calibrate the conversion errors. The behavioral simulation and measured results show that the 16-bit SAR ADC performance can be improved after the digital calibration. The prototype was fabricated in 0.18 μm CMOS process. The INL are −6/7.813 LSB, the DNL are −0.925/1.313 before calibration. After calibration, the INL are −0.813/0.938, the DNL are −0.625/0.688. The measured ENOB is 11.42 bit and SFDR is 79.95 dB before calibration, while the ENOB is 14.46 bit and SFDR is 95.65 dB after calibration.     

一种流水线ADC数字域动态可重构架构

分析流水线ADC数字域校准算法工作原理及实现电路的具体特点.为解决数字校准算法系数实时更新的问题,在PipeRench结构的基础上结合多重上下文动态可重构方式,提出了一种针对流水线ADC数字域的动态可重构电路.对该架构中的关键电路模块进行了设计并对整个电路架构进行了仿真,结果表明该架构可以实现流水线ADC数字域的动态重构.     

应用于流水线模数转换器的快速前后台组合数字校正

本文描述了一种用于流水线模数转换器的快速数字校正技术。所提出的数字校正方法利用了前台和后台校正,可以纠正由于MDAC中电容失配和运放有限增益所产生的非线性。在本文的组合校正算法中,提出了新型带有信号平移相关算法的并行数字后台校正技术,它的校正周期非常短。本文的数字校正方法以一个14位100Msps流水线模数转换器为例。本文的数字后台校正通过三种方式达到高速的收敛速度。首先,提出了改进型1.5位流水线子级,目的是在信号通路中注入大幅值的伪随机抖动信号而不产生失码;其次,在校正级输出信号进行相关运算之前先根据校正级的输入信号范围进行平移,从而使相关运算达到高速的收敛速度;最后,前端流水线子级同时进行校正,而不是逐级进行校正,从而降低数字后台校正周期。仿真结果证明组合校正具有快速的启动过程和非常短的后台校正周期。     

An efficient background calibration technique for analog-to-digital converters based on neural network

This paper introduces a background digital calibration algorithm based on neural network, which can adaptively calibrate multiple non-ideal factors in a single-channel ADC, such as gain error, mismatch, offset and harmonic distortion. It enables an efficient background calibration through a simple feed forward neural network and LM gradient descent algorithm. The simulation results show that in the case of a signal input close to the Nyquist frequency, for a 14-bit 500 MS/s prototype ADC, only about 40,000 data needed, the ENOB of the ADC can be increased from 7.81 to 13.06 and the SFDR from 49.7 dB to 106.8 dB assisted by a lower speed reference ADC.     

最小化重投影误差的手眼标定优化算法

为了减小图像噪声对手眼标定精度的影响,在传统的手眼标定算法的基础上,利用基于最小化重投影误差优化算法求解手眼标定方程.以基于矩阵直积参数化方法计算出的手眼关系矩阵为初值,以摄影测量光束平差为优化模型,最小化重投影误差为代价函数,获得最优的手眼关系标定值.实验结果证明了该方法的具有较好的稳定性和精确性,算法求解了 10次...     

一种应用于CMOS图像传感器数字双采样ADC的PGA电路

提出了一种应用于CMOS图像传感器数字双采样模数转换器(ADC)的可编程增益放大器(PGA)电路。通过增加失调采样电容,采集PGA运放和电容失配引入的失调电压,在PGA复位阶段和放大阶段进行相关双采样和放大处理,通过数字双采样ADC将两个阶段存储电压量化,并在数字域做差,降低了PGA电路引入的固定模式噪声。采用0.18μm CMOS图像传感器专用工艺进行仿真,结果表明:在输入失调电压-30~30mV变化区间,提出的PGA的输出失调电压可以降低到1mV以下,相比传统PGA输出失调电压随输入失调电压单倍线性关系而言大大降低了列固定模式噪声。     

基于DDS相位搜索的数字阵列通道幅相标校技术

在大型数字相控阵系统中,为了满足阵列增益及天线方向图特性,需要保证阵列通道的幅度和相位的一致性,而动态不一致性标校是大型阵列的标校难题。提出了一种基于直接数字频率合成（Direct Digital Synthesizer,DDS）相位搜索算法的数字相控阵通道一致性标校技术,较传统基于相关算法的标校技术,可有效降低对标校信号信噪比的要求,且可提升大规模数字阵列通道标校的效率。仿真结果表明,当信噪比等于0 dB时,采用所提算法可将幅度估计误差的均方根误差（Root Mean Square Error,RMSE）值控制在0.3 dB以内,相位估计误差的RMSE值可控制在1.5°以内,较传统算法的性能均提升了3倍。通过搭建样机评估系统,进一步验证了提出算法对数字相控阵通道一致性标校性能的提升。