Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

Low Specific On-Resistance SOI LDMOS with Non-Depleted Embedded P-Island and Dual Trench Gate

A new silicon-on-insulator(SOI) trench lateral double-diffused metal oxide semiconductor(LDMOS) with a reduced specific on-resistance R_(on),sp is presented. The structure features a non-depleted embedded p-type island(EP) and dual vertical trench gate(DG)(EP-DG SOI). First, the optimized doping concentration of drift region is increased due to the assisted depletion effect of EP. Secondly, the dual conduction channel is provided by the DG when the EP-DG SOI is in the on-state. The increased optimized doping concentration of the drift region and the dual conduction channel result in a dramatic reduction in R_(on),sp. The mechanism of the EP is analyzed,and the characteristics of R_(on),sp and breakdown voltage(BV) are discussed. Compared with conventional trench gate SOI LDMOS, the EP-DG SOI decreases R_(on),sp by 47.1% and increases BV from 196 V to 212 V at the same cell pitch by simulation.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Weak avalanche multiplication in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

In this paper, we propose an analytical avalanche multiplication model for the next generation of SiGe silicon-on-insulator (SOI) heterojunction bipolar transistors (HBTs) and consider their vertical and lateral impact ionizations for the first time. Supported by experimental data, the analytical model predicts that the avalanche multiplication governed by impact ionization shows kinks and the impact ionization effect is small compared with that of the bulk HBT, resulting in a larger base-collector breakdown voltage. The model presented in the paper is significant and has useful applications in the design and simulation of the next generation of SiGe SOI BiCMOS technology.     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.     

盖革模式下反偏压对雪崩光电二极管贯穿特性的影响

利用无源抑制技术,研究了盖革模式下雪崩光电二极管（APD）的电流一电压特性。发现光电流和暗电流的一个显著区别是暗电流不反映贯穿特性,这是光生栽流子和热载流子有不同统计分布的实验证据,也说明在盖革模式下,暗计数增加比光子探测效率增加更快的原因是由于载流子收集效率不同引起的。根据其贯穿特性适当选择盖革模式下APD的反偏压可提高单光子探测器的信噪比。     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

Analytical base–collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base--collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors (HBTs) on silicon on insulator (SOI) is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector--base bias--and shows a kink as the reverse collector--base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.     

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper for the first time, a partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) is proposed with a novel trench which improves breakdown voltage. The introduced trench in the partial buried oxide enhances peak of the electric field and is positioned in the drain side of the drift region to maximize breakdown voltage. We demonstrate that the electric field is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the trench-partial-silicon-on-insulator (T-PSOI) structure. Hence, a more uniform electric field is obtained. Two dimensional (2D) simulations show that the breakdown voltage of T-PSOI is nearly 64% higher in comparison with partial silicon on insulator (PSOI) structure and alleviate self heating effect approximately 9% and 15% in comparison with its conventional PSOI (C-PSOI) and conventional SOI (C-SOI) counterparts respectively. In addition the current of the T-PSOI, C-PSOI, conventional SOI (C-SOI), and fully depleted conventional SOI (FC-SOI) structures are 90, 82, 74, and 44 μA, respectively for a drain–source voltage V_DS = 30 V and gate–source voltage V_GS = 10 V.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

Analytical models of lateral power devices with arbitrary vertical doping profiles in the drift region

By solving the 2D Poisson's equation, analytical models are proposed to calculate the surface potential and electric field distributions of lateral power devices with arbitrary vertical doping profiles. The vertical and the lateral breakdown voltages are formulized to quantify the breakdown characteristic in completely-depleted and partially-depleted cases. A new reduced surface field (RESURF) criterion which can be used in various drift doping profiles is further derived for obtaining the optimal trade-off between the breakdown voltage and the on-resistance. Based on these models and the numerical simulation, the electric field modulation mechanism and the breakdown characteristics of lateral power devices are investigated in detail for the uniform, linear, Gaussian, and some discrete doping profiles along the vertical direction in the drift region. Then, the mentioned vertical doping profiles of these devices with the same geometric parameters are optimized, and the results show that the optimal breakdown voltages and the effective drift doping concentrations of these devices are identical, which are equal to those of the uniform-doped device, respectively. The analytical results of these proposed models are in good agreement with the numerical results and the previous experimental results, confirming the validity of the models presented here.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

Extracting dark current components and characteristics parameters for InGaAs/InP avalanche photodiodes

The dark current of separate absorption grading charge multiplication (SAGCM) InGaAs/InP avalanche photodiodes has been numerical analyzed. SRH current, TAT current, BBT current and avalanche amplification combined together as the dark current have been extracted by simulation separately. The trend of punch-through voltage and breakdown voltage have been discussed, meanwhile the influence of structure parameters also has been investigated.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

超高速脉冲晶闸管设计及特性

介绍一种超高速脉冲半导体器件,该器件属于穿通型器件,电压可达到5000V,电流上升率可以达到20kA/μs以上,根据参数调配,脉冲峰值电流可以达到数百kA。该器件采用多元胞集成结构,采用缓冲层与阳极透明层相结合的扩散技术,使其在压降和开通等方面相对于传统的晶闸管原理开关有更强的优势。并且,该超高速脉冲器件在工艺设计及实现上进行了优化,使生产条件易满足。     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.