New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor (4H-SiC MESFET) structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications.The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one-and two-dimensional Poisson’s equations.In the models,we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted.The direct-current and the alternatingcurrent performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 μm are calculated.The calculated results are in good agreement with the experimental data.The current is larger than that of the conventional structure.The cutoff frequency (fT) and the maximum oscillation frequency (f max) are 20.4 GHz and 101.6 GHz,respectively,which are higher than 7.8 GHz and 45.3 GHz of the conventional structure.Therefore,the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

改进型异质栅对深亚微米栅长碳化硅MESFET特性影响

基于器件物理分析方法,结合高场迁移率、肖特基栅势垒降低、势垒隧穿等物理模型, 分析了改进型异质栅结构对深亚微米栅长碳化硅肖特基栅场效应晶体管沟道电势、 夹断电压以及栅下电场分布的影响.通过与传统栅结构器件特性的对比表明, 异质栅结构在碳化硅肖特基栅场效应晶体管的沟道电势中引入了多阶梯分布,加强了近源端电场; 另一方面,相比于双栅器件,改进型异质栅器件沟道最大电势的位置远离源端, 因此载流子在沟道中加速更快,在一定程度上屏蔽了漏压引起的电势变化,更好抑制了短沟道效应. 此外,研究了不同结构参数的异质栅对短沟道器件特性的影响,获得了优化的设计方案, 减小了器件的亚阈值倾斜因子.为发挥碳化硅器件在大功率应用中的优势,设计了非对称异质栅结构, 改善了栅电极边缘的电场分布,提高了小栅长器件的耐压.     

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metalben semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.     

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two- dimensional Poisson’s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor (SMGFET).     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

Parameter analysis for gate metal-oxide-semiconductor structures of ion-implanted 4H silicon carbide metal-semiconductor field-effect transistors

From the theoretical analysis of the thermionic emission model of current-voltage characteristics, this paper extracts the parameters for the gate Schottky contact of two ion-implanted 4H-SiC metal-semiconductor field-effect transistors (sample A and sample B for three and four times multiple ion-implantation channel region respectively) fabricated in the experiment, including the ideality factor, the series resistance, the zero-field barrier height, the interface oxide capacitance, the interface state density distribution, the neutral level of interface states and the fixed space charge density. The methods to improve the interface of the ion-implanted Schottky contact are given at last.     

Model and analysis of drain induced barrier lowering effect for 4H--SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL (drain induced barrier lowering) effect for short channel 4H--SiC metal semiconductor field effect transistors (MESFETs). An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H--SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a (channel length/channel depth) ratio, drain applied voltage V_DS and channel doping concentration N_D, thus providing a good basis for the design and modelling of short channel 4H--SiC MESFETs device.     

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metal-semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Channel length scaling and the impact of metal gate work function on the performance of double gate-metal oxide semiconductor field-effect transistors

In this paper, we study the effects of short channel on double gate MOSFETs. We evaluate the variation of the threshold voltage, the subthreshold slope, the leakage current and the drain-induced barrier lowering when channel length L _CH decreases. Furthermore, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson-Schrödinger solver in two dimensions over the entire device. A good agreement with numerical simulation results is obtained.     

阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.     

A new physics-based self-heating effect model for 4H-SiC MESFETs

A new self-heating effect model for 4H-SiC MESFETs is proposed based on a combination of an analytical and a computer aided design (CAD) oriented drain current model. The circuit oriented expressions of 4H-SiC low-field electron mobility and in-complete ionization rate, which are related to temperature, are presented in this model, which are used to estimate the self-heating effect of 4H-SiC MESFETs. The verification of the present model is made, and the good agreement between simulated results and measured data of DC I-V curves with the self-heating effect is obtained.     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.     

量子点浮置栅量子线沟道三栅结构单电子场效应管存储特性的数值模拟

通过建立二维薛定谔方程和泊松方程数值模型,对基于硅量子点浮置栅和硅量子线沟道三栅结构单电子场效应管(FET)存储特性进行了研究.通过在不同尺寸、栅压和不同写入电荷条件下,对硅量子线沟道中电子浓度的二维有限元自洽数值求解,研究了在纳米尺度下硅量子线沟道中量子限制效应和电荷分布对于器件特性的影响.模拟结果发现,沟道的导通阈值电压随着尺寸的缩小而提高,并随浮置栅内存储的电子数目的增加而明显升高.然而,这样的增加趋势在受到纳米尺度沟道中高电荷密度的影响下将出现非线性饱和趋势.进一步研究发现,当沟道尺寸较小时,沟道 关键词： 三栅单电子FET存储器 量子效应 薛定谔方程 泊松方程     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

A high mobility C60 field-effect transistor with an ultrathin pentacene passivation layer and bathophenanthroline/metal bilayer electrodes

C₆₀ field-effect transistor (OFET) with a mobility as high as 5.17 cm²/V·s is fabricated. In our experiment, an ultrathin pentacene passivation layer on poly-(methyl methacrylate) (PMMA) insulator and a bathophenanthroline (Bphen)/Ag bilayer electrode are prepared. The OFET shows a significant enhancement of electron mobility compared with the corresponding device with a single PMMA insultor and an Ag electrode. By analysing the C₆₀ film with atomic force microscopy and X-ray diffraction techniques, it is shown that the pentacene passivation layer can contribute to C₆₀ film growth with the large grain size and significantly improve crystallinity. Moreover, the Bphen buffer layer can reduce the electron contact barrier from Ag electrodes to C₆₀ film efficiently.