A new simplified threshold-voltage model for n-MOSFETs with nonuniformly doped substrate and its application to MOSFET's miniaturization

The formulation, verification, and application of a new simplified 2-D threshold voltage model for n-MOSFETs with nonuniformly doped substrate profile are provided, in which the averaged normal field at the Si/SiO/sub 2/ interface in the active channel is quoted from a simplified solution of two-dimensional Poisson equation using the Green function technique. Starting with the expression of this average normal field, a simple threshold-voltage model for short-channel n-MOSFETs with nonuniformly doped substrate profile is explicitly expressed in terms of device structures and terminal voltages by considering parabolic source-drain boundary potentials. Moreover, the effects of the junction depth on the threshold voltage are examined in detail. It is shown that the DIBL effect cannot be completely eliminated by simply increasing the substrate doping concentration. Comparisons among developed model, 2-D numerical analysis, and experimental data have been made and the accuracy of the developed analytical model has been verified. In addition, a direct extension of our model to the case of uniformly doped substrates leads to a new constraint equation for device miniaturization.<>     

A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates

A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.     

Calculation of threshold voltage in nonuniformly doped MOSFET's

A simple algorithm is presented that is based on a semi-empirical modification of a closed form expression for the inversion charge, to allow the calculation of the so-called extrapolated threshold voltage versus source-substrate bias in nonuniformly doped MOSFET's. This algorithm is suitable for incorporation into process simulation computer programs like SUPREM. It is demonstrated, by comparison to exact calculations and to measurements, that the algorithm gives accurate values of extrapolated threshold voltage even for cases where junctions are present in the MOSFET substrate under the gate.     

A new threshold voltage model for deep-submicron MOSFETs with nonuniform substrate dopings

A simple but accurate threshold voltage model for deep-submicron MOSFETs with nonuniform dopings is described in this paper. In this model, a simplified quasi-delta substrate doping profile is used to approximate the nonuniformity. We apply a hyperbola function to avoid the discontinuous problem at the boundary between different doping regions. By adjusting the parameter δ, the actual gradual doping profile can be obtained. A substrate-bias dependent model of short channel effect is also introduced which describes the reduction of substrate-bias effect in deep-submicron devices. The model developed is in good agreement with two-dimensional numerical simulation.     

On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate

Expressions for the flat-band voltage V_FB and threshold voltage V_T for MOS devices with polysilicon gate and nonuniformly doped substrate are given. The role of metal-semiconductor contacts and the assumptions involved in the analysis are discussed. Both V_FB and V_T have three extra terms over the conventional expressions, two terms result from nonuniform doping and one is due to a voltage drop in the gate produced by space charge. Contrasts are made to devices with metal gates and uniformly doped substrates. The commonly used expression for mobile channel charge in terms of gate voltage is clarified.     

Threshold voltage of nonuniformly doped MOS structures

The minimum of the HF capacitance and the threshold voltage, for nonuniformly doped MOS structures, are calculated by means of an analytical model containing an adequate definition of the condition of strong surface inversion. The results obtained for profiles piling up close to the surface are in excellent agreement with those obtained by a numerical integration of Poisson's equation.     

A new two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs

Based on two-dimensional (2D) Poisson potential solution, a compact, analytical model for threshold voltage in cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs is successfully derived. The minimum surface potential _min,surface is used to develop the threshold voltage model. Besides decreasing the characteristic factor, both the thin silicon body and gate oxide can reduce the threshold voltage roll-off simultaneously. It is also found that the threshold voltage shift is dependent on the scaling factor of λ₁L. The high scaling factor is preferred to alleviate threshold voltage degradation.     

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structuresfor high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V_th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V_th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length     

一种简化衬底模型的SOI MOS变容管模型

提出一种适用于反型层RF SOI MOS 变容管行为表征模型。在BSIMSOI的基础上,模型采用简化的衬底模型和外围射频寄生模型来表征变容管的射频寄生效应,同时采用T、π互转的方式提出参数提取算法。模型最终应用到华虹宏力SOI工艺提供的不同栅指,每栅指长度为1.6um、宽度为5 um的MOS变容管器件,并且在15GHz以下,模型与测量数据的CV、QV以及S参数有较好的拟合。在高频情况下,模型既保证了精度又解决了参数提取困难等问题。     

A new boron implantation model suitable for analytical modeling of threshold voltage of MOSFETs

The boron implantation profile in silicon is usually simulated by the Pearson-IV distribution function with some modifications, as in SUPREM. But this function is complex from the point of view of analytical modeling. New functions which fit very well with SUPREM simulated implantation profiles for boron in silicon have been proposed in this paper. These functions, being analytically integrable, allow us to formulate accurate analytical models of threshold voltages of MOSFETs with implanted channels. In this paper models for the threshold voltages of both long channel and short channel NMOSFETs have been presented. For the long channel case, the results agree very well with those obtained from numerical computations with considerable saving of computation time. The results of the short channel model also show good agreement with available experimental data.     

A simple model for threshold voltage of surrounding-gate MOSFET's

We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner     

An analytical threshold-voltage model of trench-isolated MOSdevices with nonuniformly doped substrates

A simple closed-form expression of the threshold voltage is developed for trench-isolated MOS (TIMOS) devices with feature size down to the deep-submicrometer range. The analytical expression is the first developed to include the nonuniform doping effect of a narrow-gate-width device. The inverse narrow width effect can be predicted analytically from the proposed model. It was derived by modeling the gate sidewall capacitance to include the two-dimensional field-induced edge fringing effect and solving the Poisson equation to include the channel implant effect at different operating backgate biases. A two-dimensional simulation program was developed, and the simulated data were used for verification of the analytical model. Good agreements between the modeled and simulated data have been achieved for a wide range of gate widths and biases. The model is well suited for the design of the basic transistor cell in DRAM circuits using trench field oxide isolation structure     

A new analysis of the threshold voltage for non-uniform ion-implant MOSFET's

An analysis for the threshold voltage of MOSFET's with a Gaussian ion-implant profile is presented. Two parameters xpand xb, which characterize the peak location and the spread of a Gaussian profile, can be arbitrarily adjusted such that even a deeply ion-implanted device can be simulated. The theory predicts a good agreement with available experimental data collected from transistors with a wide range of process parameters and also confirms the so-called anomalous short-channel effect recently observed by Nishida and Onodera [3].     

A new full-wave hybrid differential-integral approach for the investigation of multilayer structures including nonuniformly doped diffusions

A novel hybrid differential-integral approach, based on the transverse wave formulation (TWF) is presented for full-wave investigation of multilayer structures including inhomogeneous layer stacks with arbitrary doping profiles. In combining both the benefits of spatial and spectral resolutions, the TWF offers a natural framework for the implementation of multiresolution and multiscale approaches from physical considerations. The possibility of separating the transverse TE and TM components of the TWF solution is discussed. Original isolation structures based on the oxide deep-trenches technique are proposed and demonstrate significant isolation capability in the context of RF integrated-circuit applications.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements     

A new 2-D model for the potential distribution and threshold voltage of fully depleted short-channel Si-SOI MESFETs

A new two-dimensional (2-D) analytical model for the threshold voltage of a fully depleted short-channel Si-MESFETs fabricated on the silicon-on-insulator (SOI) has been presented in this paper. The 2-D potential distribution functions in the active layer of the device is approximated as a parabolic function and the 2-D Poisson's equation has been solved with suitable boundary conditions to obtain the bottom potential at the Si/oxide layer interface. The calculations have been carried out for both uniform and nonuniform doping profiles in two dimensions. The minimum bottom potential is used to monitor the drain-induced barrier lowering effect and consequently an analytical expression for the threshold voltage of the device has been derived. The numerical results for the bottom potential and threshold voltage considering a wide range of device parameters have also been presented. The model has been compared with the simulated results obtained by using the ATLAS Device Simulation Software to show the validity of the proposed model. For uniform doping profile, the numerical results have also been compared with the reported data in the literature and a good agreement is observed among the three. The proposed model is simple and easy to understand the behavior of the fully depleted short-channel SOI-MESFETs as compared to the other models reported in the literature.     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.