共查询到19条相似文献,搜索用时 58 毫秒
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设计了一种基于流水线模/数转换系统应用的低压高速CMOS全差分运算放大器。该运放采用了折叠式共源共栅放大结构与一种新型连续时间共模反馈电路相结合以达到高速度及较好的稳定性。设计基于SMIC 0.25μm CMOS标准工艺模型,在Cadence环境下对电路进行了Spectre仿真。在2.5V单电源电压下,驱动0.5pF负载时,开环增益为71.1dB,单位增益带宽为303MHz,相位裕度为52°,转换速率高达368.7V/μs,建立时间为12.4ns。 相似文献
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全差分运放中共模反馈电路的一种新接法 总被引:5,自引:1,他引:4
提出一种新的连接方法,利用一个简单的差分对,通过与差分信号共用信号通路,实现共模反馈电路,比传统方法节省了晶体管.并给出使用了这个共模反馈电路的一个高速、高增益、二级全差分运算放大器的设计实例.给出了理论分析和HSPICE的模拟结果.其共模回路的开环增益72dB,单位增益带宽34MHz,相位裕度是70°,增益裕度12dB. 相似文献
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两级运放中共模反馈电路的分析与设计 总被引:1,自引:0,他引:1
在两级共源共栅CMOS运算放大器中,设计了一种新的共模反馈电路。这种电路克服了一般共模反馈电路存在的限制输出摆幅的缺点,在稳定电路直流工作点的同时,能有效提高电路的输出摆幅。通过对共模电路结构的分析,证明了其功能原理的正确性。基于0.18μm(3V)CMOS工艺库,用Hspice软件对电路结构进行了仿真验证。结果显示,电路低频增益达到120dB,功耗不到0.24mW。 相似文献
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提出了一种降低高频噪声的前置全差分放大器.运放内部采用了两组偏置电路,一组用于单位增益缓冲器电路,一组用于放大电路.为了确保电路稳定性又不增加设计难度,将单位增益缓冲器电路与共模反馈回路结合起来.设计采用HHNEC 0.18μm BCD工艺,Cadence Spectre仿真表明,正常工作时共模反馈的环路增益84.93dB,单位增益带宽9.52MHz,相位裕度67.62°;启动时单位增益缓冲器电路的环路增益85.18dB,单位增益带宽8.93MHz,相位裕度67.2°;关断时,单位增益缓冲器电路的环路增益63.26dB,单位增益带宽2.28MHz,相位裕度88.66°.实测表明,设计降低了D类音频功放在开启和关断时的噪声. 相似文献
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This paper presents a new CMOS fully differential current feedback operational amplifier (FDCFOA). The proposed CMOS realization of the FDCFOA is based on a novel class AB fully differential buffer circuit. Besides the proposed FDCFOA circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 400 A. The applications of the FDCFOA to realize variable gain amplifier, fully differential integrator, and fourth order fully differential maximally flat low pass filter are given. The fourth order filter provides 8 dB gain and a bandwidth of 4.3 MHz to accommodate the wideband CDMA standard. The proposed FDCFOA and its applications are simulated using CMOS 0.35 m technology.Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include low voltage analog CMOS circuit design, filtering and applications suitable for VLSI.Inas Awad was born in Cairo, Egypt, in 1971. She received the Bachelor, the M.Sc. and the Ph.D. degrees in Electronics and Communications from Cairo University in 1994, 1997 and 2000, respectively. In 1995, she joined the department of Electronics and Communications, Cairo University, Fayoum-Campus as a teaching assistant and now she is an Assistant Professor at the same department. Her primary research interest is in analog circuits with particular emphasis on current-mode approach and low-voltage low-power CMOS designs. 相似文献
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采用全差分运算放大器、无源电阻以及用作可变电阻的MOS管设计实现了全差分R-MOSFET-C四阶Bessel有源低通滤波器,在所提出的电路中通过调节工作在线性区的MOS管有源电阻的阻值以抵消集成电路制造工艺过程中电阻阻值的一致性偏差,达到Bessel滤波器的群时延值得到精确设计的目的.该滤波器中所采用的全差分运算放大器不仅具备有电压共模负反馈,而且还具有电流共模负反馈,极有利于电路静态工作点的稳定.通过无源双端RLC原型低通滤波器导出的0.75μs群时延四阶Bessel滤波器,采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)、5.0V电源电压、0.5μm CMOS工艺制造,在输入信号为100kHz、2.5Vpp时,其谐波失真(THD)值低于-65dB. 相似文献
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本文通过理论分析和流片测试验证了一个应用于心电采集系统的具有较低总谐波失真(THD)的全差分VGA。该VGA采用电容反馈技术来降低系统的非线性。本系统基于SMIC 0.18-μm CMOS工艺进行设计和流片,芯片面积仅为0.11 mm2。芯片测量结果同电路后仿真结果相吻合。测试结果表明VGA以3dB的增益步长由6.17dB到43.75dB变化,其高通角频率和低通角频率分别为0.22Hz和7.9kHz;各个增益级下获得最大的THD为-59.4dB。表明了该全差分VGA具有低的THD,其主要性能指标均满足心电采集系统在UWB健康监护与遥测系统中的应用要求。 相似文献
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Giuseppe Ferri Willy Sansen Vincenzo Peluso 《Analog Integrated Circuits and Signal Processing》1998,16(1):5-15
A low-voltage fully differential CMOS operational amplifier withconstant-gmand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage. 相似文献