High throughput N-modular redundancy for error correction design of memristive stateful logic

Memristive stateful logic is one of the most promising candidates to implement an in-memory computing system that computes within the storage unit. It can eliminate the costs for the data movement in the traditional von Neumann system. However, the instability in the memristors is inevitable due to the limitation of the current fabrication technology, which incurs a great challenge for the reliability of the memristive stateful logic. In this paper, the implication of device instability on the reliability of the logic event is simulated. The mathematical relationship between logic reliability and redundancy has been deduced. By combining the mathematical relationship with the vector-matrix multiplication in a memristive crossbar array, the logic error correction scheme with high throughput has been proposed. Moreover, a universal design paradigm has been put forward for complex logic. And the circuit schematic and the flow of the scheme have been raised. Finally, a 1-bit full adder (FA) based on the NOR logic and NOT logic is simulated and the mathematical evaluation is performed. It demonstrates the scheme can improve the reliability of the logic significantly. And compared with other four error corrections, the scheme which can be suitable for all kinds of R-R logics and V-R logics has the best universality and throughput. Compared with the other two approaches which also need additional complementary metal-oxide semiconductor (CMOS) circuits, it needs fewer transistors and cycles for the error correction.     

同步时序逻辑电路设计新法

提出了一种同步时序逻辑电路设计新方法．根据触发器(FF)的基本特性，可从电路的状态转换图上直接求得触发器置位、复位函数，进而确定触发器的驱动方程．具体设计实例表明该方法简捷、高效，设计电路功能正确．     

A novel circuit design for complementary resistive switch-based stateful logic operations

Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch(CRS)-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.     

The voltage-current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage-current relationships （VCRs） between two parallel memristive circuits - a parallel memristor and capacitor circuit （the parallel MC circuit）, and a parallel memristor and inductor circuit （the parallel ML circuit） - are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and exper/mental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results.     

磁性量子元胞自动机逻辑电路的转换特性研究

本文研究了磁性量子元胞自动机反相器和择多逻辑门等基本逻辑电路在不同纳磁体厚度和间距下的转换特性.采用单畴近似LLG方程对纳磁体以及电路进行了建模和仿真,结果表明更厚的纳磁体需要更大的转换磁脉冲,大厚度纳磁体逻辑电路表现出较慢的转换;相同厚度和间距下,择多逻辑门比反相器的转换时间略长.此外,模拟结果还表明纳磁体间距对反相器的转换过程影响明显,而对择多逻辑门则影响较小. 关键词： 磁性量子元胞自动机 转换特性 厚度和间距 逻辑电路     

Luminescence-based molecular scale logic circuits

We show how a half-adder logic circuit can be implemented on one molecule for a molecule exhibiting both S₁→S₀ and S₂→S₀ fluorescence. This is achieved by using both one photon S₀→S₁ excitation and consecutive S₁→S₂ excitation and establishing logic thresholds by utilizing the laser-induced photoquenching process. We present results pertaining to rhodamine and azulene molecules, in which, for the first time, an all optical half-adder logic circuit is implemented.     

基于碳纳米管场效应管构建的纳电子逻辑电路

展示了由碳纳米管场效应管构成的三种逻辑电路，分别为单个p型碳纳米管场效应管的开关电路、由集成在同一片硅片上的单个p型碳纳米管场效应管和单个n型掺氮碳纳米管场效应管构成的互补型反相器，以及两个独立的p型碳纳米管场效应管构成的或非门. 其中p型碳纳米管场效应管以单壁碳纳米管作为沟道，而n型碳纳米管场效应管则以掺氮的多壁碳纳米管作为沟道，器件的源漏电极均为铂电极. 关键词： 碳纳米管 场效应管 逻辑电路     

基于交换作用的纳磁逻辑电路片上时钟结构研究

纳磁逻辑电路具有低功耗、非易失和可常温下制备等优点, 实现低功耗片上时钟是其集成化的必备条件. 本文提出了一种基于交换作用的纳磁逻辑电路片上时钟结构, 用载流铜导线产生的奥斯特场将铁磁体薄膜覆层进行磁化, 然后依靠铁磁体层与纳磁体界面存在的交换作用场使后者磁化方向发生翻转. 与轭式铁磁体时钟用外磁场控制纳磁体磁化方向相比, 该方案在功耗方面降低了5/6, 时钟边界杂散场强度降低了2/3, 达到降低功耗、减轻串扰的目的. 此外, 采用微磁仿真进一步验证了该时钟结构上的纳磁体逻辑阵列可以实现逻辑功能. 关键词： 纳磁逻辑 片上时钟 交换作用     

基于模拟电路的新型忆感器等效模型

本文首先利用光敏电阻阻值的可控性, 建立了磁通控制型忆阻器的等效电路模型. 通过对忆感器和忆阻器间转换关系的分析, 采用模拟电子元器件设计了磁通控制型忆感器的实用等效电路模型, 给出了理论分析并结合Pspice软件进行了仿真验证. 忆感器等效电路模型的韦安关系展现出典型的非线性磁滞回线特性. 最后, 运用实验手段研究了正弦波和三角波两种典型电压信号激励下忆感器与RC串联后电路的动态特征, 证明了本文提出忆感器等效电路模型的有效性. 关键词： 忆阻器 忆感器 磁滞回线特性 Pspice     

蔡氏电路的功能全同电路与拓扑等效电路及其设计方法

基于经典蔡氏电路方程的电容电压与电感电流变量及其状态方程归一化特点,提出了三种标度化、优化的电路设计方法:一种是方程变量都为电压的5运放电源限幅蔡氏电路,便于大规模集成;两种二极管非线性构成的功能全同蔡氏电路,与限幅非线性电路优势互补,可供大规模集成的细胞神经网络系统设计;同时,给出了与蔡氏电路为微分同胚电路的优化三次方蔡氏电路.各电路设计方法适用于以三折线为主的三次型混沌电路.最后,将本文提出的电路设计方法应用于混沌保密通信,实验表明该方法具有实用性和一定的应用价值.     

Defect-oriented testing of Josephson logic circuits and systems

In this paper, defect-oriented testing of low temperature superconducting Josephson logic systems is used as a basis for structural test generation. This requires the investigation of processing defects using defect monitors and the development of fault models. Inductive fault analysis techniques play an important role in this approach. By means of fault injection in the JSIM circuit simulator, the most effective test signals can be derived which can subsequently be used for test-generator hardware in a built-in self test environment.     

BILED／BILD组合回路的光学逻辑运算

利用激光二极管或发光二极管混合双稳态回路(BILD/BILED)的组合,得到了光学多稳态,光学异或逻辑门和光学R-S触发器.这种光电子学的逻辑回路与大规模集成技术完全相容,因此有希望应用于光学信息处理,光通信和光计算.     

双路可编程光学多重成像并行二值逻辑处理器

基于多重成像原理，在本文中提出一种光学并行图像逻辑处理系统。对输入图案用两个正像和两个补偿进行编码。通过光调制器控制，可以实现逻辑操作的实时可编程。而且，该系统可以通过控制一组四个偏振片的状态实现独立的双输出逻辑通道，每一个输出通道各有十六种逻辑功能。文中也给出了实验结果。     

一个分数阶忆阻器模型及其简单串联电路的特性

忆阻器是具有时间记忆特性的非线性电阻. 经典HP TiO₂忆阻器模型的忆阻值为此前通过忆阻器电流的时间积分, 即记忆没有损失. 而最近研究证实HP TiO₂ 线性忆阻器掺杂层厚度不能等于零或者器件整体厚度, 导致器件的记忆有损失. 基于此发现, 本文首先提出了一个阶数介于0 与1间的分数阶HP TiO₂ 线性忆阻器模型, 研究了当受到周期外激励时, 分数阶导数的阶数对其忆阻值动态范围和输出电压动态幅值的影响规律, 推导出了磁滞旁瓣面积的计算公式. 结果表明, 分数阶导数阶数对磁滞回线的形状及所围成区域面积有重要影响. 特别地, 在外激频率大于1时, 分数阶忆阻器的记忆强度达到最大. 然后讨论了此分数阶忆阻器与电容或电感串联组成的单口网络的伏安特性. 结果表明, 在周期激励驱动时, 随着分数阶导数阶数的变化, 此分数阶忆阻器与电容的串联电路呈现出纯电容电路与忆阻电路的转换, 而它与电感的串联电路则呈现出纯电感电路与忆阻电路的转换.     

Digital synthesis of programmable photonic integrated circuits

Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular synthesis algorithm often only accounts for a specific function with a specific cell configuration.In this paper,we try to synthesize the programmable waveguide mesh to support multiple configurations with a more general digital signal processing platform.To show the feasibility of this technique,photonic waveguide meshes in different configurations(square,triangular and hexagonal meshes)are designed to realize optical signal interleaving with arbitrary duty cycles.The digital signal processing(DSP)approach offers an effective pathway for the establishment of a general design platform for the software-defined programmable photonic integrated circuits.The use of well-developed DSP techniques and algorithms establishes a link between optical and electrical signals and makes it convenient to realize the computer-aided design of optics–electronics hybrid systems.     

Multiple-valued logic unit design using polarization-encoded optical shadow-casting

An efficient technique for the design of multiple-valued logic circuits using polarization-encoded optical shadow-casting is presented. As an illustration, a trinary full subtracter is designed using this technique. The resulting logic unit is compared with those obtained by using other algorithms.     

一种最简的并行忆阻器混沌系统

在提出的一种压控忆阻器的基础上, 构造了最简的并联忆阻器混沌系统, 分析其动力学特性, 得到了该系统的Lyapunov指数和Lyapunov维数, 给出了时域波形、相图、Lyapunov指数谱、分岔图、Poincaré映射等. 利用EWB软件设计了该新混沌系统的振荡电路并进行了仿真实验. 研究结果表明, 忆阻器的i-v特性在参数的变化时, 并不保持斜“8”字形, 会变为带尾巴的扇形. 该混沌系统与磁控忆阻器混沌系统不同, 系统只有一个平衡点, 初始条件在系统能振荡的情况下不影响系统状态. 电路实验仿真结果和数值仿真具有很好的一致性, 证实了该系统的存在性和物理上可实现性. 关键词： 忆阻器 混沌电路 并联 动力学行为     

Optical implementation of butterfly interconnection and digital logic operation by grating

Optical butterfly interconnection and four primary optical perallel logic opera-tions are implemented by means of phase grating and liquid crystal light valve (LCLV),whichoffers a simple new scheme for implementing optical butterfly interconnections and digitalcomputations.     

Fuzzy logic classifier design for air targets recognition based on HRRP

The paper describes a fuzzy logic classifier (FLC) to achieve the recognition for air targets. We first acquire the high range resolution profiles (HRRP) of three types of air targets from the measurements. We extract two typical features, namely, the length of the air targets and the difference between adjacent two HRRP based on HRRP from the measurements. Then we design the FLC to synthesize the two characters and identify the type of air targets. Simulation results show that our FLC can achieve the function of target recognition with a high ratio of recognition and also show a robust performance to some extent.     

Monolithic circuits with epitaxial graphene/silicon carbide transistors

A concept is presented that uses epitaxial graphene on silicon carbide (SiC) for digital circuits. It uses graphene as a metal and the underlying substrate SiC as semiconductor. On the base of transistors with excellent switching behavior, Inverter and NAND operation is demonstrated.