Effect of atomic passivation at Ni-MoS2 interfaces on contact behaviors

Recently, spintronics devices using MoS₂ and ferromagnetic electrode have been in the spotlight. However, strong Fermi level pinning (FLP) is known to occur between MoS₂ and ferromagnetic electrode, resulting in a large Schottky barrier height (SBH), which makes it difficult to inject electron from ferromagnetic electrode to semiconductor. To resolve this problem, we study the reduction of FLP occurring between two materials by investigating the effect of atomic passivation at Ni-MoS₂ interfaces on contact behaviors. Such atomic passivation can reduce the FLP and magnetic moments induced at S atoms of MoS₂. Especially, the largest decrease in the FLP occurs in the case of H atom passivation. Besides, the N, O, and F atom passivation confirms the possibility of ohmic contact, indicated from small SBHs (~0.2 eV). As a result, the SBH and thus the efficiency of the device can be controlled by atomic passivation at metal-semiconductor interfaces.     

High energy electron radiation effect on Ni/4H-SiC SBD and Ohmic contact

The Ni/4H-SiC Schottky barrier diodes (SBDs) and transfer length method (TLM) test patterns of Ni/4H-SiC Ohmic contacts were fabricated, and irradiated with 1~MeV electrons up to a dose of 3.43× 10¹⁴~e/cm^-2. After radiation, the forward currents of the SBDs at 2~V decreased by about 50%, and the reverse currents at -200~V increased by less than 30%. Schottky barrier height (φ _B ) of the Ni/4H-SiC SBD increased from 1.20~eV to 1.21~eV under 0~V irradiation bias, and decreased from 1.25~eV to 1.19~eV under -30~V irradiation bias. The degradation of φ _B could be explained by the variation of interface states of Schottky contacts. The on-state resistance (R_s) and the reverse current increased with the dose, which can be ascribed to the radiation defects in bulk material. The specific contact resistance (\rho_c) of the Ni/SiC Ohmic contact increased from 5.11× 10⁵~Ωega.cm² to 2.97× 10^-4~Ωega.cm².     

Top contact organic field effect transistors fabricated using a photolithographic process

This paper proposes an effective method of fabricating top contact organic field effect transistors by using a pho-tolithographic process.The semiconductor layer is protected by a passivation layer.Through photolithographic and etching processes,parts of the passivation layer are etched off to form source/drain electrode patterns.Combined with conventional evaporation and lift-off techniques,organic field effect transistors with a top contact are fabricated suc-cessfully,whose properties are comparable to those prepared with the shadow mask method and one order of magnitude higher than the bottom contact devices fabricated by using a photolithographic process.     

Bandgap opening in MoTe2 thin flakes induced by surface oxidation

Recently, the layered transition metal dichalcogenide 1T′-MoTe₂ has generated considerable interest due to their superconducting and non-trivial topological properties. Here, we present a systematic study on 1T′-MoTe₂ single-crystal and exfoliated thin-flakes by means of electrical transport, scanning tunnelling microscope (STM) measurements and band structure calculations. For a bulk sample, it exhibits large magneto-resistance (MR) and Shubnikov–de Hass oscillations in ρ_xx and a series of Hall plateaus in ρ_xy at low temperatures. Meanwhile, the MoTe₂ thin films were intensively investigated with thickness dependence. For samples, without encapsulation, an apparent transition from the intrinsic metallic to insulating state is observed by reducing thickness. In such thin films, we also observed a suppression of the MR and weak anti-localization (WAL) effects. We attributed these effects to disorders originated from the extrinsic surface chemical reaction, which is consistent with the density functional theory (DFT) calculations and in-situ STM results. In contrast to samples without encapsulated protection, we discovered an interesting superconducting transition for those samples with hexagonal Boron Nitride (h-BN) film protection. Our results indicate that the metallic or superconducting behavior is its intrinsic state, and the insulating behavior is likely caused by surface oxidation in few layer 1T′-MoTe₂ flakes.     

电磁轨道发射器连续发射的滑动电接触

从滑动电接触电阻大小的角度,详细分析了在时序放电条件下,两颗重约为5 g的电枢,以速度为1 000 m/s,166 Hz连续发射试验。通过近似计算电流所流经轨道电阻及电枢体电阻所产生的温升,对滑动电接触电阻的影响。结果表明:连续发射运行模式下,受轨道表面温度上升的影响,第二发电枢的滑动接触电阻略高于第一发电枢的滑动接触电阻,表面滑动电接触性能受到温升的影响,在两连发的发射情况下,其影响虽不是很大,但多发高频连续发射就必须考虑热管理问题。      

组合材料方法研究膜厚对Ni/SiC电极接触性质的影响

采用组合材料方法研究了金属Ni膜厚对Ni/SiC接触性质的影响.16个膜厚均为18 nm的Ni/SiC电极具有较为一致的肖特基接触性质;膜厚从10 nm增加到160 nm,肖特基接触的电流-电压（I-V）曲线随膜厚发生显著变化.分析表明这种变化源于膜厚对理想因子n和有效势垒高度Ф_B的影响.1000℃快速退火后,这些肖特基接触都转变为欧姆接触,Ni₂Si是主要的生成物.I-V曲线测 关键词： 碳化硅 肖特基接触 欧姆接触 组合材料方法     

不同封装方式对肖特基二极管高频性能的影响

肖特基二极管是太赫兹接收机的关键器件,通过在高频下对不同封装形式的肖特基二极管进行建模仿真,研究不同封装方式对肖特基二极管性能的影响。首先通过建立肖特基二极管的仿真模型,在高频结构仿真软件HFSS中对肖特基二极管在0~120 GHz频段进行仿真,得到该肖特基二极管的S参数,并对S参数仿真结果和实测结果进行对比,证明了该二极管模型的准确性。然后分别建立肖特基二极管的普通封装模型和肖特基二极管的倒装芯片(flip-chip)封装模型,并对这两种封装模型进行仿真,得到其在两种不同封装结构下的S参数,进而对两种不同封装方式的S参数的-3 dB带宽以及相位一致性进行对比分析。最终,对应用于太赫兹波段的肖特基二极管由于封装不同而带来的带宽以及相位的区别及其成因进行分析,论证了flip-chip封装更适合应用于太赫兹波段的肖特基二极管,与普通封装相比,该封装在高频下对肖特基二极管的电性能有比较大的改进。     

不同封装方式对肖特基二极管高频性能的影响

肖特基二极管是太赫兹接收机的关键器件,通过在高频下对不同封装形式的肖特基二极管进行建模仿真,研究不同封装方式对肖特基二极管性能的影响。首先通过建立肖特基二极管的仿真模型,在高频结构仿真软件HFSS中对肖特基二极管在0~120GHz频段进行仿真,得到该肖特基二极管的S参数,并对S参数仿真结果和实测结果进行对比,证明了该二极管模型的准确性。然后分别建立肖特基二极管的普通封装模型和肖特基二极管的倒装芯片(flip-chip)封装模型,并对这两种封装模型进行仿真,得到其在两种不同封装结构下的S参数,进而对两种不同封装方式的S参数的-3dB带宽以及相位一致性进行对比分析。最终,对应用于太赫兹波段的肖特基二极管由于封装不同而带来的带宽以及相位的区别及其成因进行分析,论证了flipchip封装更适合应用于太赫兹波段的肖特基二极管,与普通封装相比,该封装在高频下对肖特基二极管的电性能有比较大的改进。     

电磁轨道发射器连续发射的滑动电接触

从滑动电接触电阻大小的角度,详细分析了在时序放电条件下,两颗重约为5 g的电枢,以速度为1 000 m/s,166 Hz连续发射试验。通过近似计算电流所流经轨道电阻及电枢体电阻所产生的温升,对滑动电接触电阻的影响。结果表明:连续发射运行模式下,受轨道表面温度上升的影响,第二发电枢的滑动接触电阻略高于第一发电枢的滑动接触电阻,表面滑动电接触性能受到温升的影响,在两连发的发射情况下,其影响虽不是很大,但多发高频连续发射就必须考虑热管理问题。      

Double threshold behaviour of I－V characteristics of CoSi2/Si Schottky contacts

The forward current－voltage (I－V) characteristics of polycrystalline CoSi₂/n-Si(100) Schottky contacts have been measured in a wide temperature range. At low temperatures (≤200K), a plateau-like section is observed in the I－V characteristics around 10^-4A·cm^-2. The current in the small bias region significantly exceeds that expected by the model based on thermionic emission (TE) and a Gaussian distribution of Schottky barrier height (SBH). Such a double threshold behaviour can be explained by the barrier height inhomogeneity, i.e. at low temperatures the current through some patches with low SBH dominates at small bias region. With increasing bias voltage, the Ohmic effect becomes important and the current through the whole junction area exceeds the patch current, thus resulting in a plateau-like section in the I－V curves at moderate bias. For the polycrystalline CoSi₂/Si contacts studied in this paper, the apparent ideality factor of the patch current is much larger than that calculated from the TE model taking the pinch-off effect into account. This suggests that the current flowing through these patches is of the tunnelling type, rather than the thermionic emission type. The experimental I－V characteristics can be fitted reasonably well in the whole temperature region using the model based on tunnelling and pinch-off.     

Analysis of the effect of sidewall on the performance of 6H-SiC Schottky barrier source/drain NMOSFETs

Between source/drain and gate of SiC Schottky barrier source/drain MOSFET (SiC SBSD-MOSFET), there must be a sidewall as isolation. The width of sidewall strongly affects on the device performance. In this paper the effect of sidewall on the performance of 6H-SiC SBSD-NMOSFET is simulated with the 2D simulator MEDICI. The simulated results show that a sidewall with width less than 0.1μm slightly affects the device performance. However, when the width of sidewall exceeds 0.1μm, the conduction does not occur until the drain voltage is high enough and saturation current sharply decreases. The effect of the sidewall on device performance can be reduced by decreasing the doping concentration in the epitaxial layer.     

二硫化钨/石墨烯异质结的界面相互作用及其肖特基调控的理论研究

采用第一性原理方法研究了二硫化钨/石墨烯异质结的界面结合作用以及电子性质,结果表明在二硫化钨/石墨烯异质结中,其界面相互作用是微弱的范德瓦耳斯力.能带计算结果显示异质结中二硫化钨和石墨烯各自的电子性质得到了保留,同时,由于石墨烯的结合作用,二硫化钨呈现出n型半导体.通过改变界面的层间距可以调控二硫化钼/石墨烯异质结的肖特基势垒类型,层间距增大,肖特基将从p型转变为n型接触.三维电荷密度差分图表明,负电荷聚集在二硫化钨附近,正电荷聚集在石墨烯附近,从而在界面处形成内建电场.肖特基势垒变化与界面电荷流动密切相关,平面平均电荷密度差分图显示,随着层间距逐渐增大,界面电荷转移越来越弱,且空间电荷聚集区位置向石墨烯层方向靠近,导致费米能级向上平移,证实了肖特基势垒随着层间距的增加由p型接触向n型转变.本文的研究结果将为二维范德瓦耳斯场效应管的设计与制作提供指导.     

Influence of Schottky drain contacts on the strained AlGaN barrier layer of AlGaN/AlN/GaN heterostructure field-effect transistors

Rectangular Schottky drain AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with different gate contact areas and conventional AlGaN/AlN/GaN HFETs as control were both fabricated with same size. It was found there is a significant difference between Schottky drain AlGaN/AlN/GaN HFETs and the control group both in drain series resistance and in two-dimensional electron gas (2DEG) electron mobility in the gate-drain channel. We attribute this to the different influence of Ohmic drain contacts and Schottky drain contacts on the strained AlGaN barrier layer. For conventional AlGaN/AlN/GaN HFETs, annealing drain Ohmic contacts gives rise to a strain variation in the AlGaN barrier layer between the gate contacts and the drain contacts, and results in strong polarization Coulomb field scattering in this region. In Schottky drain AlGaN/AlN/GaN HFETs, the strain in the AlGaN barrier layer is distributed more regularly.     

硅基二氧化钒相变薄膜电学特性研究

本文以原子层沉积超薄氧化铝(Al₂ O₃)为过渡层, 采用射频反应磁控溅射法在硅半导体基片上制备了颗粒致密并具有(011)择优取向的二氧化钒(VO₂)薄膜. 该薄膜具有显著的绝缘体–金属相变特性, 相变电阻变化超过3 个数量级, 热滞回线宽度约为6℃. 基于VO₂薄膜构建了平面二端器件并测试了不同温度下I-V曲线, 观测到超过2个数量级的电流跃迁幅度, 显示了优越的电致相变特性. 室温下电致相变阈值电压为8.6 V, 电致相变弛豫电压宽度约0.1 V. 随着温度升高到60℃, 其电致相变所需要的阈值电压减小到2.7 V. 本实验制备的VO₂薄膜在光电存储、开关、太赫兹调控器件中具有广泛的应用价值.     

Effect of diode size and series resistance on barrier height and ideality factor in nearly ideal Au/n type-GaAs micro Schottky contact diodes

Small high-quality Au/n type-GaAs Schottky barrier diodes (SBDs) with low reverse leakage current are produced using lithography. Their effective barrier heights (BHs) and ideality factors from current-voltage (I-V) characteristics are measured by a Pico ampere meter and home-built I-V instrument. In spite of the identical preparation of the diodes there is a diode-to-diode variation in ideality factor and barrier height parameters. Measurement of topology of a surface of a thin metal film with atomic force microscope (AFM) shows that Au-n type-GaAS SD consists of a set of parallel-connected micro and nanocontacts diodes with sizes approximately in a range of 100-200 nm. Between barrier height and ideality factor there is an inversely proportional dependency. With the diameter of contact increasing from 5 μm up to 200 μm, the barrier height increases from 0.833 up to 0.933 eV and its ideality factor decreases from 1.11 down to 1.006. These dependencies show the reduction of the contribution of the peripheral current with the diameter of contact increasing. We find the effect of series resistance on barrier height and ideality factor.     

Effect of nanopatches on electrical behavior of Ni/n-type Si Schottky diode

Topological surface measurement of thin metal film using a conducting probe atomic force microscope (C-AFM) shows that thin metal film deposited on Ni/n-Si Schottky diode (SD) consists of patches. These patches are sets of parallel connected and electrically cooperating nano-contacts of size between 50 and 100nm. Every individual patch acts as an individual diode with different I-V curve, barrier height (BH) and ideality factor (n). Between these diodes or patches, there are spot field distributions; the patches with different local work functions are in direct electric contact with surrounding patches. As a result, a potential difference between surfaces of patches, the so-called electrostatic spot field E_f, is formed. It is shown that in real metal-semiconductor (MS) contacts, patches with quite different configurations, various geometrical sizes and local work functions are randomly distributed on the surface of metal; hence direction and intensity of spot field are non-uniformly distributed along the surface of metal. There is a linear dependence between barrier height and ideality factor, which is the consequence of reduction of distance of the maximum of BH from the interface. This dependency is the sign of reduction of contribution of a peripheral current.     

电场诱导二氧化钒绝缘-金属相变的研究进展

二氧化钒(VO_2)是电子强关联体系的典型代表,其晶体结构在特定阈值的温度、电场、光照和压力等物理场作用下会发生由单斜金红石结构向四方金红石结构的可逆转变,从而引发绝缘-金属相变.其中,电场诱导VO_2绝缘-金属相变后的电导率可提高2-5个数量级,在可重构缝隙天线、太赫兹辐射以及智能电磁防护材料等领域具有广阔的应用前景,成为近年来人们的研究热点.首先,简要概述了VO_2发生绝缘-金属相变时晶体结构和能带结构的变化,进而从电场诱导VO_2绝缘-金属相变的研究方法、响应时间、临界阈值场强调控以及相变机理几个方面系统总结和评述了近年来国内外学者在该领域的重要发现和研究进展.最后,指出了当前VO_2绝缘-金属相变研究存在的问题,并展望了未来的发展方向.     

接触电阻对碳纳米管场发射的影响

基于改进的悬浮球模型,计算了碳纳米管和衬底间的接触电阻存在时碳纳米管顶端的局域电场, 并结合Fowler-Nordheim (F-N)场发射规律研究了接触电阻对碳纳米管场发射的影响.研究表明,接触电阻的存在,在高电场区域接触电阻抑制了碳纳米管的电子场发射,导致在高电场区域出现电流饱和及FN直线偏折现象.其原因可归结为接触电阻使得在碳纳米管顶端的局域电场相对于没有接触电阻时相对地减少. 关键词： 碳纳米管 场发射 接触电阻 电流饱和     

Effects of surface roughness on the electrical characteristics of ZnO nanowire field effect transistors

We have systematically investigated the effects of surface roughness on the electrical characteristics of ZnO nanowire field effect transistors (FETs) before and after passivation by poly (methyl metahacrylate) (PMMA), a polymer-insulating layer. To control the surface morphology of ZnO nanowires, ZnO nanowires were grown by the vapor transport method on two different substrates, namely, an Au-catalyzed sapphire and an Au-catalyzed ZnO film/sapphire. ZnO nanowires grown on the Au-catalyzed sapphire substrate had smooth surfaces, whereas those grown on the Au-catalyzed ZnO film had rough surfaces. Electrical characteristics such as the threshold voltage shift and transconductance before and after passivation were strongly affected by the surface morphology of ZnO nanowires.     

Effect of heating on electrical transport in AlGaN/GaN Schottky barrier diodes on Si substrate

Thermal properties of the AlGaN/GaN Schottky barrier diodes were investigated, using a pulsed-IV measurement technique. The thermally degraded mobility in the DC-bias configuration was restored, when the pulse-bias voltages were applied. It was observed that heat generation was minimized, using a pulse width of 500 ns and pulse period of 10 ms. For the SBDs consisting of 5 μm of anode–cathode distance, on-resistance measured by the pulse-IV and DC-IV were 1.6 and 6.2 Ω-mm, respectively. We also demonstrated the device-width dependence of the thermal properties of the SBDs. We found that the performance of the power devices can be greatly influenced by the heat generation.